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1 parent 9b3ea47 commit 777abb2

2 files changed

Lines changed: 5 additions & 3 deletions

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lib/Dialect/FIRRTL/Transforms/InferWidths.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2097,7 +2097,8 @@ FailureOr<bool> InferenceTypeUpdate::updateOperation(Operation *op) {
20972097
auto lhsWidth = lhsType.getBitWidthOrSentinel();
20982098
auto rhsWidth = rhsType.getBitWidthOrSentinel();
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if (lhsWidth >= 0 && rhsWidth >= 0 && lhsWidth < rhsWidth) {
2100-
con.emitOpError("destination ") << lhsType << " is not as wide as the source " << rhsType;
2100+
con.emitOpError("destination ")
2101+
<< lhsType << " is not as wide as the source " << rhsType;
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return failure();
21022103
}
21032104
return anyChanged;

lib/Dialect/FIRRTL/Transforms/LowerCHIRRTL.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -407,8 +407,9 @@ void LowerCHIRRTLPass::replaceMem(Operation *cmem, StringRef name,
407407

408408
// If both widths are known and index is wider, insert explicit truncation
409409
if (addrWidth >= 0 && indexWidth >= 0 && indexWidth > addrWidth) {
410-
indexValue = TailPrimOp::create(portBuilder, indexValue,
411-
indexWidth - addrWidth).getResult();
410+
indexValue =
411+
TailPrimOp::create(portBuilder, indexValue, indexWidth - addrWidth)
412+
.getResult();
412413
}
413414
emitConnect(portBuilder, address, indexValue);
414415
// Sequential+Read ports have a more complicated "enable inference".

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