[FIRRTL] EliminateWires: preserve sv.attributes when converting WireOp to NodeOp

When LowerAnnotations processes firrtl.AttributeAnnotation (the mechanism
used by Chisel's addAttribute()), it sets sv.attributes on the FIRRTL
WireOp. EliminateWires then converts single-writer passive WireOps to
NodeOps without copying sv.attributes, causing attributes like mark_debug
to be silently dropped before LowerToHW runs.

Copy sv.attributes from the WireOp to the replacement NodeOp, matching
the existing pattern in LowerToHW.cpp for RegOp and RegResetOp.

Assisted-by: vscode/eicp:Claude Opus 4.6

Author: bheneffe

lib/Dialect/FIRRTL/Transforms/EliminateWires.cpp

@@ -15,6 +15,7 @@
 
 #include "circt/Dialect/FIRRTL/FIRRTLOps.h"
 #include "circt/Dialect/FIRRTL/Passes.h"
+#include "circt/Dialect/SV/SVAttributes.h"
 #include "circt/Support/Debug.h"
 #include "mlir/IR/Dominance.h"
 #include "mlir/IR/ImplicitLocOpBuilder.h"
@@ -87,6 +88,12 @@ void EliminateWiresPass::runOnOperation() {
     auto node = NodeOp::create(builder, writer.getSrc(), wire.getName(),
                                wire.getNameKind(), wire.getAnnotations(),
                                wire.getInnerSymAttr(), wire.getForceable());
+    // Preserve sv.attributes (e.g. mark_debug) set by LowerAnnotations from
+    // firrtl.AttributeAnnotation. Without this, the attributes are silently
+    // dropped when a WireOp is converted to a NodeOp, causing addAttribute()
+    // annotations to never appear in the emitted SV.
+    if (auto svAttrs = sv::getSVAttributes(wire))
+      sv::setSVAttributes(node, svAttrs);
     wire.replaceAllUsesWith(node);
     wire.erase();
     writer.erase();

test/Dialect/FIRRTL/eliminate-wires.mlir

@@ -3,7 +3,7 @@
 firrtl.circuit "TopLevel" {
 
   // CHECK-LABEL: @TopLevel
-  firrtl.module @TopLevel(in %source: !firrtl.uint<1>, 
+  firrtl.module @TopLevel(in %source: !firrtl.uint<1>,
                              out %sink: !firrtl.uint<1>) {
     // CHECK-NOT: firrtl.wire
     %w = firrtl.wire : !firrtl.uint<1>
@@ -26,4 +26,19 @@ firrtl.circuit "TopLevel" {
     // CHECK-NEXT:  %b = firrtl.node %[[inv]] : !firrtl.uint<3>
     // CHECK-NEXT:  %a = firrtl.node %b : !firrtl.uint<3>
   }
+
+  // CHECK-LABEL: @SvAttributesPreserved
+  // Verify that sv.attributes set on a wire are propagated to the replacement
+  // NodeOp. Previously EliminateWires dropped sv.attributes, causing
+  // firrtl.AttributeAnnotation (Chisel's addAttribute()) to produce no output
+  // in emitted SV.
+  firrtl.module private @SvAttributesPreserved(in %source: !firrtl.uint<1>,
+                                               out %sink: !firrtl.uint<1>) {
+    // CHECK-NOT: firrtl.wire
+    // CHECK: %w = firrtl.node
+    // CHECK-SAME: sv.attributes = [#sv.attribute<"mark_debug = \22true\22">]
+    %w = firrtl.wire {sv.attributes = [#sv.attribute<"mark_debug = \"true\"">]} : !firrtl.uint<1>
+    firrtl.matchingconnect %w, %source : !firrtl.uint<1>
+    firrtl.matchingconnect %sink, %w : !firrtl.uint<1>
+  }
 }