add squash pass in the pipeline

Author: nanjo712

lib/Firtool/CMakeLists.txt

@@ -11,6 +11,7 @@ add_circt_library(CIRCTFirtool
   CIRCTOMTransforms
   CIRCTSeqToSV
   CIRCTSimToSV
+  CIRCTSimTransforms
   CIRCTSeqTransforms
   CIRCTSVTransforms
   CIRCTTransforms

lib/Firtool/Firtool.cpp

@@ -14,6 +14,7 @@
 #include "circt/Dialect/OM/OMPasses.h"
 #include "circt/Dialect/SV/SVPasses.h"
 #include "circt/Dialect/Seq/SeqPasses.h"
+#include "circt/Dialect/Sim/SimPasses.h"
 #include "circt/Dialect/Verif/VerifPasses.h"
 #include "circt/Support/Passes.h"
 #include "circt/Transforms/Passes.h"
@@ -307,6 +308,9 @@ LogicalResult firtool::populateLowFIRRTLToHW(mlir::PassManager &pm,
                                        opt.getVerificationFlavor(),
                                        opt.shouldLowerToCore()));
 
+  if (opt.shouldLowerToCore())
+    pm.addNestedPass<hw::HWModuleOp>(sim::createSquashSimTriggered());
+
   if (!opt.shouldDisableOptimization()) {
     auto &modulePM = pm.nest<hw::HWModuleOp>();
     modulePM.addPass(mlir::createCSEPass());

test/firtool/lower-to-core.fir

@@ -25,24 +25,16 @@ circuit LowerToCore:
 ; CHECK-DAG: verif.clocked_assert %pred if %enable, posedge [[CLK]] : i1
 ; CHECK-DAG: [[FMT:%.+]] = sim.fmt.dec %x signed : i4
 ; CHECK: [[MSG:%.+]] = sim.fmt.concat ([[LIT]], [[FMT]], [[NL]])
+; CHECK: [[FMTFILE2:%.+]] = sim.fmt.concat ([[LITFILE1]], [[FMT]], [[LITFILE2]])
+; CHECK: [[STDERR:%.+]] = sim.stderr_stream
 ; CHECK: sim.triggered %clock if %enable {
 ; CHECK-NEXT:   sim.proc.print [[MSG]]
-; CHECK-NEXT: }
-; CHECK: sim.triggered %clock if %enable {
 ; CHECK-NEXT:   [[FILE1:%.+]] = sim.get_file [[FMTFILE1]]
 ; CHECK-NEXT:   sim.proc.print [[MSG]] to [[FILE1]]
-; CHECK-NEXT: }
-; CHECK: [[FMTFILE2:%.+]] = sim.fmt.concat ([[LITFILE1]], [[FMT]], [[LITFILE2]])
-; CHECK: sim.triggered %clock if %enable {
 ; CHECK-NEXT:   [[FILE2:%.+]] = sim.get_file [[FMTFILE2]]
 ; CHECK-NEXT:   sim.proc.print [[MSG]] to [[FILE2]]
-; CHECK-NEXT: }
-; CHECK: sim.triggered %clock if %enable {
 ; CHECK-NEXT:   [[FILE3:%.+]] = sim.get_file [[FMTFILE2]]
 ; CHECK-NEXT:   sim.flush [[FILE3]]
-; CHECK-NEXT: }
-; CHECK: [[STDERR:%.+]] = sim.stderr_stream
-; CHECK: sim.triggered %clock if %enable {
 ; CHECK-NEXT:   sim.flush [[STDERR]]
 ; CHECK-NEXT: }
 ; CHECK-NOT: sv.assert