[SV] Add pass to hide non-synthesizable ops (#10479)

Add `--sv-mask-non-synthesizable`, a late SV pass that hides concurrent and property assert/assume/cover ops from synthesis. Three modes (`delete`, `ifdef`) and a configurable macro name. All modes are idempotent across re-runs. Operates on `mlir::ModuleOp` and processes each `hw.module` in parallel. Wired into the PyCDE final lowering pipeline so its output is acceptable to Quartus and other tools that reject SVA constructs. This is the configurable-pass alternative to the always-on `ifdef SYNTHESIS` guards in `LowerVerifToSV` that were tried in #10387 and reverted.

Closes #10378.

Assisted-by: vscode:Claude Opus 4.7

Author: teqdruid

frontends/PyCDE/src/pycde/system.py

@@ -473,6 +473,7 @@ def _run_pass_list(self, pass_list, pass_run_name, module=None, debug=False):
       "builtin.module(lower-comb)",
       "builtin.module(hw.module(lower-verif-to-sv))",
       "builtin.module(cse, canonicalize, cse)",
+      "builtin.module(sv-mask-non-synthesizable)",
       "builtin.module(hw.module(prettify-verilog), hw.module(hw-cleanup))",
       "builtin.module(msft-export-tcl{{tops={tops} tcl-file={tcl_file}}})"
   ]

include/circt/Dialect/SV/SVPasses.h

@@ -18,6 +18,15 @@
 namespace circt {
 namespace sv {
 
+/// Selects how `sv-mask-non-synthesizable` hides matched ops from
+/// synthesis-bound SystemVerilog output.
+enum class MaskNonSynthesizableMode {
+  /// Erase the matched ops.
+  Delete,
+  /// Wrap the matched ops in `` `ifndef SYNTHESIS `` ... `` `endif ``.
+  Ifdef,
+};
+
 #define GEN_PASS_DECL
 #include "circt/Dialect/SV/SVPasses.h.inc"
 

include/circt/Dialect/SV/SVPasses.td

@@ -130,4 +130,44 @@ def HWEliminateInOutPorts : Pass<"hw-eliminate-inout-ports",
   ];
 }
 
+def SVMaskNonSynthesizable : Pass<"sv-mask-non-synthesizable",
+                                  "mlir::ModuleOp"> {
+  let summary = "Hide non-synthesizable SV ops from synthesis tools";
+  let description = [{
+    This pass hides a fixed set of `sv` ops that are not generally
+    synthesizable (concurrent and property assertions) from the
+    SystemVerilog output. Two masking modes are supported:
+
+    * `delete`: erase the matched ops entirely.
+    * `ifdef`: wrap each matched op individually in
+      `` `ifndef <macro> `` ... `` `endif `` (using `sv.ifdef` or
+      `sv.ifdef.procedural` as appropriate). A matching `sv.macro.decl` is
+      created at the top of the module if one is not already present. The
+      macro name is configurable via the `macro` option (default
+      `SYNTHESIS`).
+
+    The pass is intended to run as one of the last passes before `ExportVerilog`
+    so we only have to know about a smaller number of ops but before the
+    HWCleanup pass (which will merge the sv.ifdef ops where it can). The set of
+    masked op names is hard-coded in the pass implementation. Both modes are
+    idempotent.
+  }];
+
+  let dependentDialects = ["circt::sv::SVDialect"];
+  let options = [
+    Option<"mode", "mode", "::circt::sv::MaskNonSynthesizableMode",
+           "::circt::sv::MaskNonSynthesizableMode::Ifdef",
+           "How to mask the matched ops",
+           [{::llvm::cl::values(
+             clEnumValN(::circt::sv::MaskNonSynthesizableMode::Delete,
+                        "delete", "Erase the matched ops"),
+             clEnumValN(::circt::sv::MaskNonSynthesizableMode::Ifdef,
+                        "ifdef",
+                        "Wrap matched ops in `ifndef SYNTHESIS")
+           )}]>,
+    Option<"macro", "macro", "std::string", "\"SYNTHESIS\"",
+           "Macro name used by `ifdef` mode">
+  ];
+}
+
 #endif // CIRCT_DIALECT_SV_SVPASSES

lib/Dialect/SV/Transforms/CMakeLists.txt

@@ -5,6 +5,7 @@ add_circt_dialect_library(CIRCTSVTransforms
   HWLegalizeModules.cpp
   PrettifyVerilog.cpp
   HWExportModuleHierarchy.cpp
+  SVMaskNonSynthesizable.cpp
   SVTraceIVerilog.cpp
   HWEliminateInOutPorts.cpp
 

lib/Dialect/SV/Transforms/SVMaskNonSynthesizable.cpp

@@ -0,0 +1,194 @@
+//===- SVMaskNonSynthesizable.cpp - Mask non-synthesizable SV ops ---------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This pass hides a fixed set of `sv` operations that are not generally
+// synthesizable (concurrent and property assertions) from the SystemVerilog
+// output. It supports two masking modes:
+//
+//   * `delete`: erase the matched ops.
+//   * `ifdef` : wrap each matched op individually in an
+//               `sv.ifdef`/`sv.ifdef.procedural` whose else region holds the
+//               moved op, plus a single `sv.macro.decl @SYNTHESIS` at the top
+//               of the module if absent.
+//
+//===----------------------------------------------------------------------===//
+
+#include "circt/Dialect/HW/HWOps.h"
+#include "circt/Dialect/SV/SVAttributes.h"
+#include "circt/Dialect/SV/SVOps.h"
+#include "circt/Dialect/SV/SVPasses.h"
+#include "circt/Support/Namespace.h"
+#include "circt/Support/ProceduralRegionTrait.h"
+#include "circt/Support/Utils.h"
+#include "mlir/IR/Builders.h"
+#include "mlir/Pass/Pass.h"
+#include "llvm/ADT/TypeSwitch.h"
+
+namespace circt {
+namespace sv {
+#define GEN_PASS_DEF_SVMASKNONSYNTHESIZABLE
+#include "circt/Dialect/SV/SVPasses.h.inc"
+} // namespace sv
+} // namespace circt
+
+using namespace circt;
+using namespace circt::sv;
+
+//===----------------------------------------------------------------------===//
+// Helpers
+//===----------------------------------------------------------------------===//
+
+/// Returns true if `op` is one of the SV ops we mask.
+static bool isMaskedOp(Operation *op) {
+  return isa<sv::AssertConcurrentOp, sv::AssumeConcurrentOp,
+             sv::CoverConcurrentOp, sv::AssertPropertyOp, sv::AssumePropertyOp,
+             sv::CoverPropertyOp>(op);
+}
+
+/// If `op` is an `sv.ifdef`/`sv.ifdef.procedural` whose macro matches
+/// `expectedMacro`, returns its else region; otherwise returns nullptr. Used
+/// to identify the region that need not be re-wrapped in `ifdef` mode.
+static Region *getMatchingIfDefElseRegion(Operation *op,
+                                          StringRef expectedMacro) {
+  return llvm::TypeSwitch<Operation *, Region *>(op)
+      .Case<sv::IfDefOp, sv::IfDefProceduralOp>([&](auto ifdef) -> Region * {
+        if (ifdef.getCond().getName() != expectedMacro)
+          return nullptr;
+        return &ifdef.getElseRegion();
+      })
+      .Default(static_cast<Region *>(nullptr));
+}
+
+/// Resolve the symbol name to use for the `sv.macro.decl` referenced by
+/// `ifdef` mode's `sv.ifdef` ops. Returns the existing decl's sym_name if a
+/// `sv.macro.decl` whose Verilog identifier matches `verilogName` already
+/// exists at top level; otherwise returns a fresh sym_name that does not
+/// collide with any existing top-level symbol (which may differ from
+/// `verilogName` if a non-`sv.macro.decl` symbol of that name is present).
+/// `created` is set to true iff the returned name belongs to a decl that
+/// the caller still needs to materialize.
+static StringAttr resolveMacroSymName(mlir::ModuleOp moduleOp,
+                                      StringRef verilogName, bool &created) {
+  for (auto decl : moduleOp.getOps<sv::MacroDeclOp>()) {
+    if (decl.getMacroIdentifier() == verilogName) {
+      created = false;
+      return decl.getSymNameAttr();
+    }
+  }
+  Namespace ns;
+  ns.add(moduleOp);
+  StringRef name = ns.newName(verilogName);
+  created = true;
+  return StringAttr::get(moduleOp.getContext(), name);
+}
+
+/// `delete` mode: walk the block and erase every masked op.
+static void processBlockDelete(Block &block) {
+  block.walk([&](Operation *op) {
+    if (isMaskedOp(op))
+      op->erase();
+  });
+}
+
+/// Wrap a single masked op in its own `sv.ifdef`/`sv.ifdef.procedural`. Picks
+/// the procedural variant based on the enclosing region.
+static void maskOpByIfdef(Operation *op, StringRef macro) {
+  OpBuilder builder(op);
+  Location loc = op->getLoc();
+
+  // Passing a non-null `elseCtor` is what triggers the builder to create an
+  // else block.
+  Block *elseBlock;
+  if (isInProceduralRegion(op))
+    elseBlock =
+        sv::IfDefProceduralOp::create(builder, loc, macro,
+                                      /*thenCtor=*/{}, /*elseCtor=*/[]() {})
+            .getElseBlock();
+  else
+    elseBlock = sv::IfDefOp::create(builder, loc, macro, /*thenCtor=*/{},
+                                    /*elseCtor=*/[]() {})
+                    .getElseBlock();
+
+  // Move the op into the else block.
+  op->moveBefore(elseBlock, elseBlock->end());
+}
+
+/// `ifdef` mode: wrap each masked op in its own
+/// `sv.ifdef`/`sv.ifdef.procedural`. Recurse into nested regions of non-masked
+/// ops, but skip recursion into the else region of a matching
+/// `sv.ifdef @<macro>` -- those ops are already guarded.
+static bool processBlockIfdef(Block &block, StringRef macro) {
+  bool changed = false;
+  // `make_early_inc_range` lets us move the current op out of `block` inside
+  // the loop body without invalidating the iterator.
+  for (Operation &op : llvm::make_early_inc_range(block)) {
+    if (isMaskedOp(&op)) {
+      maskOpByIfdef(&op, macro);
+      changed = true;
+      continue;
+    }
+    Region *guardedElseRegion = getMatchingIfDefElseRegion(&op, macro);
+    for (Region &region : op.getRegions()) {
+      if (&region == guardedElseRegion)
+        continue;
+      for (Block &nested : region)
+        changed |= processBlockIfdef(nested, macro);
+    }
+  }
+  return changed;
+}
+
+//===----------------------------------------------------------------------===//
+// Pass
+//===----------------------------------------------------------------------===//
+
+namespace {
+struct SVMaskNonSynthesizablePass
+    : public circt::sv::impl::SVMaskNonSynthesizableBase<
+          SVMaskNonSynthesizablePass> {
+  using Base::Base;
+  void runOnOperation() override;
+};
+} // namespace
+
+void SVMaskNonSynthesizablePass::runOnOperation() {
+  mlir::ModuleOp moduleOp = getOperation();
+
+  // For `ifdef` mode, resolve the symbol name to use for the macro decl
+  // up front.
+  StringAttr macroSymName;
+  bool macroDeclNeedsCreation = false;
+  if (mode == MaskNonSynthesizableMode::Ifdef)
+    macroSymName = resolveMacroSymName(moduleOp, macro, macroDeclNeedsCreation);
+
+  StringRef passDownMacro =
+      macroSymName ? macroSymName.getValue() : StringRef();
+  // Each `hw.module`'s body is independent: `processBlock*` only mutates ops
+  // inside the module it's called on.
+  SmallVector<hw::HWModuleOp> hwModules(moduleOp.getOps<hw::HWModuleOp>());
+  unsigned numChanged =
+      transformReduce(&getContext(), hwModules, /*init=*/0u, std::plus<>(),
+                      [&](hw::HWModuleOp hwModule) -> unsigned {
+                        Block &body = *hwModule.getBodyBlock();
+                        switch (mode) {
+                        case MaskNonSynthesizableMode::Delete:
+                          processBlockDelete(body);
+                          return 0;
+                        case MaskNonSynthesizableMode::Ifdef:
+                          return processBlockIfdef(body, passDownMacro) ? 1 : 0;
+                        }
+                        llvm_unreachable("all modes handled");
+                      });
+
+  if (mode == MaskNonSynthesizableMode::Ifdef && numChanged > 0 &&
+      macroDeclNeedsCreation) {
+    auto builder = OpBuilder::atBlockBegin(moduleOp.getBody());
+    sv::MacroDeclOp::create(builder, moduleOp.getLoc(), macroSymName,
+                            /*args=*/ArrayAttr{}, builder.getStringAttr(macro));
+  }
+}