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[CIR] Backport Standardize element type name in Array and Vector Types #1591

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Apr 28, 2025
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[CIR] Backport Standardize element type name in Array and Vector Types #1591

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2 changes: 1 addition & 1 deletion clang/include/clang/CIR/Dialect/IR/CIROpenCLAttrs.td
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Original file line number Diff line number Diff line change
Expand Up @@ -86,7 +86,7 @@ def OpenCLKernelMetadataAttr
mlir::cast<cir::IntType>(t).isSigned();
};
return isCIRSignedIntType(hintQTy) ||
(hintEltQTy && isCIRSignedIntType(hintEltQTy.getEltType()));
(hintEltQTy && isCIRSignedIntType(hintEltQTy.getElementType()));
}
}];

Expand Down
6 changes: 3 additions & 3 deletions clang/include/clang/CIR/Dialect/IR/CIROps.td
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Expand Up @@ -3124,7 +3124,7 @@ def GetMethodOp : CIR_Op<"get_method"> {

def VecInsertOp : CIR_Op<"vec.insert", [Pure,
TypesMatchWith<"argument type matches vector element type", "vec", "value",
"cast<VectorType>($_self).getEltType()">,
"cast<VectorType>($_self).getElementType()">,
AllTypesMatch<["result", "vec"]>]> {

let summary = "Insert one element into a vector object";
Expand Down Expand Up @@ -3153,7 +3153,7 @@ def VecInsertOp : CIR_Op<"vec.insert", [Pure,

def VecExtractOp : CIR_Op<"vec.extract", [Pure,
TypesMatchWith<"type of 'result' matches element type of 'vec'", "vec",
"result", "cast<VectorType>($_self).getEltType()">]> {
"result", "cast<VectorType>($_self).getElementType()">]> {

let summary = "Extract one element from a vector object";
let description = [{
Expand Down Expand Up @@ -3208,7 +3208,7 @@ def VecCreateOp : CIR_Op<"vec.create", [Pure]> {

def VecSplatOp : CIR_Op<"vec.splat", [Pure,
TypesMatchWith<"type of 'value' matches element type of 'result'", "result",
"value", "cast<VectorType>($_self).getEltType()">]> {
"value", "cast<VectorType>($_self).getElementType()">]> {

let summary = "Convert a scalar into a vector";
let description = [{
Expand Down
26 changes: 13 additions & 13 deletions clang/include/clang/CIR/Dialect/IR/CIRTypes.td
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Original file line number Diff line number Diff line change
Expand Up @@ -350,18 +350,18 @@ def CIR_ArrayType : CIR_Type<"Array", "array",
`CIR.array` represents C/C++ constant arrays.
}];

let parameters = (ins "mlir::Type":$eltType, "uint64_t":$size);
let parameters = (ins "mlir::Type":$elementType, "uint64_t":$size);

let builders = [
TypeBuilderWithInferredContext<(ins
"mlir::Type":$eltType, "uint64_t":$size
"mlir::Type":$elementType, "uint64_t":$size
), [{
return $_get(eltType.getContext(), eltType, size);
return $_get(elementType.getContext(), elementType, size);
}]>,
];

let assemblyFormat = [{
`<` $eltType `x` $size `>`
`<` $elementType `x` $size `>`
}];
}

Expand All @@ -378,18 +378,18 @@ def CIR_VectorType : CIR_Type<"Vector", "vector",
element type and the number of elements.
}];

let parameters = (ins "mlir::Type":$eltType, "uint64_t":$size);
let parameters = (ins "mlir::Type":$elementType, "uint64_t":$size);

let builders = [
TypeBuilderWithInferredContext<(ins
"mlir::Type":$eltType, "uint64_t":$size
"mlir::Type":$elementType, "uint64_t":$size
), [{
return $_get(eltType.getContext(), eltType, size);
return $_get(elementType.getContext(), elementType, size);
}]>,
];

let assemblyFormat = [{
`<` $eltType `x` $size `>`
`<` $elementType `x` $size `>`
}];
}

Expand Down Expand Up @@ -588,9 +588,9 @@ def IntegerVector : Type<
And<[
CPred<"::mlir::isa<::cir::VectorType>($_self)">,
CPred<"::mlir::isa<::cir::IntType>("
"::mlir::cast<::cir::VectorType>($_self).getEltType())">,
"::mlir::cast<::cir::VectorType>($_self).getElementType())">,
CPred<"::mlir::cast<::cir::IntType>("
"::mlir::cast<::cir::VectorType>($_self).getEltType())"
"::mlir::cast<::cir::VectorType>($_self).getElementType())"
".isPrimitive()">
]>, "!cir.vector of !cir.int"> {
}
Expand All @@ -600,9 +600,9 @@ def SignedIntegerVector : Type<
And<[
CPred<"::mlir::isa<::cir::VectorType>($_self)">,
CPred<"::mlir::isa<::cir::IntType>("
"::mlir::cast<::cir::VectorType>($_self).getEltType())">,
"::mlir::cast<::cir::VectorType>($_self).getElementType())">,
CPred<"::mlir::cast<::cir::IntType>("
"::mlir::cast<::cir::VectorType>($_self).getEltType())"
"::mlir::cast<::cir::VectorType>($_self).getElementType())"
".isSignedPrimitive()">
]>, "!cir.vector of !cir.int"> {
}
Expand All @@ -612,7 +612,7 @@ def FPVector : Type<
And<[
CPred<"::mlir::isa<::cir::VectorType>($_self)">,
CPred<"::mlir::isa<::cir::SingleType, ::cir::DoubleType>("
"::mlir::cast<::cir::VectorType>($_self).getEltType())">,
"::mlir::cast<::cir::VectorType>($_self).getElementType())">,
]>, "!cir.vector of !cir.fp"> {
}

Expand Down
9 changes: 5 additions & 4 deletions clang/lib/CIR/CodeGen/CIRGenBuilder.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -19,7 +19,8 @@ mlir::Value CIRGenBuilderTy::maybeBuildArrayDecay(mlir::Location loc,
if (arrayTy) {
auto addrSpace = ::mlir::cast_if_present<cir::AddressSpaceAttr>(
arrayPtrTy.getAddrSpace());
cir::PointerType flatPtrTy = getPointerTo(arrayTy.getEltType(), addrSpace);
cir::PointerType flatPtrTy =
getPointerTo(arrayTy.getElementType(), addrSpace);
return create<cir::CastOp>(loc, flatPtrTy, cir::CastKind::array_to_ptrdecay,
arrayPtr);
}
Expand Down Expand Up @@ -81,8 +82,8 @@ void CIRGenBuilderTy::computeGlobalViewIndicesFromFlatOffset(
};

if (auto ArrayTy = mlir::dyn_cast<cir::ArrayType>(Ty)) {
int64_t EltSize = Layout.getTypeAllocSize(ArrayTy.getEltType());
SubType = ArrayTy.getEltType();
int64_t EltSize = Layout.getTypeAllocSize(ArrayTy.getElementType());
SubType = ArrayTy.getElementType();
const auto [Index, NewOffset] = getIndexAndNewOffset(Offset, EltSize);
Indices.push_back(Index);
Offset = NewOffset;
Expand Down Expand Up @@ -124,7 +125,7 @@ uint64_t CIRGenBuilderTy::computeOffsetFromGlobalViewIndices(
assert(idx < (int64_t)sTy.getMembers().size());
typ = sTy.getMembers()[idx];
} else if (auto arTy = dyn_cast<cir::ArrayType>(typ)) {
typ = arTy.getEltType();
typ = arTy.getElementType();
offset += layout.getTypeAllocSize(typ) * idx;
} else {
llvm_unreachable("NYI");
Expand Down
6 changes: 3 additions & 3 deletions clang/lib/CIR/CodeGen/CIRGenBuilder.h
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Original file line number Diff line number Diff line change
Expand Up @@ -405,7 +405,7 @@ class CIRGenBuilderTy : public cir::CIRBaseBuilderTy {
cir::VectorType
getExtendedOrTruncatedElementVectorType(cir::VectorType vt, bool isExtended,
bool isSigned = false) {
auto elementTy = mlir::dyn_cast_or_null<cir::IntType>(vt.getEltType());
auto elementTy = mlir::dyn_cast_or_null<cir::IntType>(vt.getElementType());
assert(elementTy && "expected int vector");
return cir::VectorType::get(isExtended
? getExtendedIntTy(elementTy, isSigned)
Expand Down Expand Up @@ -534,7 +534,7 @@ class CIRGenBuilderTy : public cir::CIRBaseBuilderTy {
cir::BoolType, cir::IntType, cir::CIRFPTypeInterface>(ty))
return true;
if (mlir::isa<cir::VectorType>(ty)) {
return isSized(mlir::cast<cir::VectorType>(ty).getEltType());
return isSized(mlir::cast<cir::VectorType>(ty).getElementType());
}
assert(0 && "Unimplemented size for type");
return false;
Expand Down Expand Up @@ -904,7 +904,7 @@ class CIRGenBuilderTy : public cir::CIRBaseBuilderTy {
createVecShuffle(mlir::Location loc, mlir::Value vec1, mlir::Value vec2,
llvm::ArrayRef<mlir::Attribute> maskAttrs) {
auto vecType = mlir::cast<cir::VectorType>(vec1.getType());
auto resultTy = cir::VectorType::get(getContext(), vecType.getEltType(),
auto resultTy = cir::VectorType::get(getContext(), vecType.getElementType(),
maskAttrs.size());
return CIRBaseBuilderTy::create<cir::VecShuffleOp>(
loc, resultTy, vec1, vec2, getArrayAttr(maskAttrs));
Expand Down
49 changes: 25 additions & 24 deletions clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2093,7 +2093,7 @@ static mlir::Value emitArmLdrexNon128Intrinsic(unsigned int builtinID,
/// and the same vector size.
static cir::VectorType getSignChangedVectorType(CIRGenBuilderTy &builder,
cir::VectorType vecTy) {
auto elemTy = mlir::cast<cir::IntType>(vecTy.getEltType());
auto elemTy = mlir::cast<cir::IntType>(vecTy.getElementType());
elemTy = elemTy.isSigned() ? builder.getUIntNTy(elemTy.getWidth())
: builder.getSIntNTy(elemTy.getWidth());
return cir::VectorType::get(elemTy, vecTy.getSize());
Expand All @@ -2102,7 +2102,7 @@ static cir::VectorType getSignChangedVectorType(CIRGenBuilderTy &builder,
static cir::VectorType
getHalfEltSizeTwiceNumElemsVecType(CIRGenBuilderTy &builder,
cir::VectorType vecTy) {
auto elemTy = mlir::cast<cir::IntType>(vecTy.getEltType());
auto elemTy = mlir::cast<cir::IntType>(vecTy.getElementType());
elemTy = elemTy.isSigned() ? builder.getSIntNTy(elemTy.getWidth() / 2)
: builder.getUIntNTy(elemTy.getWidth() / 2);
return cir::VectorType::get(elemTy, vecTy.getSize() * 2);
Expand All @@ -2111,9 +2111,9 @@ getHalfEltSizeTwiceNumElemsVecType(CIRGenBuilderTy &builder,
static cir::VectorType
castVecOfFPTypeToVecOfIntWithSameWidth(CIRGenBuilderTy &builder,
cir::VectorType vecTy) {
if (mlir::isa<cir::SingleType>(vecTy.getEltType()))
if (mlir::isa<cir::SingleType>(vecTy.getElementType()))
return cir::VectorType::get(builder.getSInt32Ty(), vecTy.getSize());
if (mlir::isa<cir::DoubleType>(vecTy.getEltType()))
if (mlir::isa<cir::DoubleType>(vecTy.getElementType()))
return cir::VectorType::get(builder.getSInt64Ty(), vecTy.getSize());
llvm_unreachable(
"Unsupported element type in getVecOfIntTypeWithSameEltWidth");
Expand Down Expand Up @@ -2148,7 +2148,7 @@ static mlir::Value emitNeonShiftVector(CIRGenBuilderTy &builder,
llvm::SmallVector<mlir::Attribute> vecAttr{
vecTy.getSize(),
// ConstVectorAttr requires cir::IntAttr
cir::IntAttr::get(vecTy.getEltType(), shiftAmt)};
cir::IntAttr::get(vecTy.getElementType(), shiftAmt)};
cir::ConstVectorAttr constVecAttr = cir::ConstVectorAttr::get(
vecTy, mlir::ArrayAttr::get(builder.getContext(), vecAttr));
return builder.create<cir::ConstantOp>(loc, constVecAttr);
Expand All @@ -2172,7 +2172,8 @@ static mlir::Value emitNeonRShiftImm(CIRGenFunction &cgf, mlir::Value shiftVec,
mlir::Location loc) {
CIRGenBuilderTy &builder = cgf.getBuilder();
int64_t shiftAmt = getIntValueFromConstOp(shiftVal);
int eltSize = cgf.CGM.getDataLayout().getTypeSizeInBits(vecTy.getEltType());
int eltSize =
cgf.CGM.getDataLayout().getTypeSizeInBits(vecTy.getElementType());

shiftVec = builder.createBitcast(shiftVec, vecTy);
// lshr/ashr are undefined when the shift amount is equal to the vector
Expand All @@ -2185,7 +2186,7 @@ static mlir::Value emitNeonRShiftImm(CIRGenFunction &cgf, mlir::Value shiftVec,
// Right-shifting a signed value by its size is equivalent
// to a shift of size-1.
--shiftAmt;
shiftVal = builder.getConstInt(loc, vecTy.getEltType(), shiftAmt);
shiftVal = builder.getConstInt(loc, vecTy.getElementType(), shiftAmt);
}
return emitCommonNeonShift(builder, loc, vecTy, shiftVec, shiftVal,
false /* right shift */);
Expand All @@ -2195,7 +2196,7 @@ static mlir::Value emitNeonRShiftImm(CIRGenFunction &cgf, mlir::Value shiftVec,
static void vecExtendIntValue(CIRGenFunction &cgf, cir::VectorType argVTy,
mlir::Value &arg, mlir::Location loc) {
CIRGenBuilderTy &builder = cgf.getBuilder();
cir::IntType eltTy = mlir::dyn_cast<cir::IntType>(argVTy.getEltType());
cir::IntType eltTy = mlir::dyn_cast<cir::IntType>(argVTy.getElementType());
assert(mlir::isa<cir::IntType>(arg.getType()) && eltTy);
// The constant argument to an _n_ intrinsic always has Int32Ty, so truncate
// it before inserting.
Expand Down Expand Up @@ -2366,22 +2367,22 @@ mlir::Value CIRGenFunction::emitCommonNeonBuiltinExpr(
case NEON::BI__builtin_neon_vabsq_v: {
mlir::Location loc = getLoc(e->getExprLoc());
ops[0] = builder.createBitcast(ops[0], vTy);
if (mlir::isa<cir::SingleType, cir::DoubleType>(vTy.getEltType())) {
if (mlir::isa<cir::SingleType, cir::DoubleType>(vTy.getElementType())) {
return builder.create<cir::FAbsOp>(loc, ops[0]);
}
return builder.create<cir::AbsOp>(loc, ops[0]);
}
case NEON::BI__builtin_neon_vmovl_v: {
cir::VectorType dTy = builder.getExtendedOrTruncatedElementVectorType(
vTy, false /* truncate */,
mlir::cast<cir::IntType>(vTy.getEltType()).isSigned());
mlir::cast<cir::IntType>(vTy.getElementType()).isSigned());
// This cast makes sure arg type conforms intrinsic expected arg type.
ops[0] = builder.createBitcast(ops[0], dTy);
return builder.createIntCast(ops[0], ty);
}
case NEON::BI__builtin_neon_vmovn_v: {
cir::VectorType qTy = builder.getExtendedOrTruncatedElementVectorType(
vTy, true, mlir::cast<cir::IntType>(vTy.getEltType()).isSigned());
vTy, true, mlir::cast<cir::IntType>(vTy.getElementType()).isSigned());
ops[0] = builder.createBitcast(ops[0], qTy);
// It really is truncation in this context.
// In CIR, integral cast op supports vector of int type truncating.
Expand All @@ -2401,7 +2402,7 @@ mlir::Value CIRGenFunction::emitCommonNeonBuiltinExpr(
llvm::SmallVector<mlir::Value, 2> mulOps(ops.begin() + 1, ops.end());
cir::VectorType srcVty = builder.getExtendedOrTruncatedElementVectorType(
vTy, false, /* truncate */
mlir::cast<cir::IntType>(vTy.getEltType()).isSigned());
mlir::cast<cir::IntType>(vTy.getElementType()).isSigned());
ops[1] = emitNeonCall(builder, {srcVty, srcVty}, mulOps,
"aarch64.neon.sqdmull", vTy, getLoc(e->getExprLoc()));
ops.resize(2);
Expand Down Expand Up @@ -2437,7 +2438,7 @@ mlir::Value CIRGenFunction::emitCommonNeonBuiltinExpr(
cir::VectorType resTy =
(builtinID == NEON::BI__builtin_neon_vqdmulhq_lane_v ||
builtinID == NEON::BI__builtin_neon_vqrdmulhq_lane_v)
? cir::VectorType::get(vTy.getEltType(), vTy.getSize() * 2)
? cir::VectorType::get(vTy.getElementType(), vTy.getSize() * 2)
: vTy;
cir::VectorType mulVecT =
GetNeonType(this, NeonTypeFlags(neonType.getEltType(), false,
Expand Down Expand Up @@ -2479,7 +2480,7 @@ mlir::Value CIRGenFunction::emitCommonNeonBuiltinExpr(
mlir::Location loc = getLoc(e->getExprLoc());
cir::VectorType srcTy = builder.getExtendedOrTruncatedElementVectorType(
vTy, false /* truncate */,
mlir::cast<cir::IntType>(vTy.getEltType()).isSigned());
mlir::cast<cir::IntType>(vTy.getElementType()).isSigned());
ops[0] = builder.createBitcast(ops[0], srcTy);
// The following cast will be lowered to SExt or ZExt in LLVM.
ops[0] = builder.createIntCast(ops[0], vTy);
Expand All @@ -2489,7 +2490,7 @@ mlir::Value CIRGenFunction::emitCommonNeonBuiltinExpr(
mlir::Location loc = getLoc(e->getExprLoc());
cir::VectorType srcTy = builder.getExtendedOrTruncatedElementVectorType(
vTy, true /* extended */,
mlir::cast<cir::IntType>(vTy.getEltType()).isSigned());
mlir::cast<cir::IntType>(vTy.getElementType()).isSigned());
ops[0] = builder.createBitcast(ops[0], srcTy);
ops[0] = emitCommonNeonShift(builder, loc, srcTy, ops[0], ops[1], false);
return builder.createIntCast(ops[0], vTy);
Expand Down Expand Up @@ -2530,7 +2531,7 @@ mlir::Value CIRGenFunction::emitCommonNeonBuiltinExpr(
}
case NEON::BI__builtin_neon_vpadd_v:
case NEON::BI__builtin_neon_vpaddq_v: {
intrincsName = mlir::isa<mlir::FloatType>(vTy.getEltType())
intrincsName = mlir::isa<mlir::FloatType>(vTy.getElementType())
? "aarch64.neon.faddp"
: "aarch64.neon.addp";
break;
Expand Down Expand Up @@ -2619,7 +2620,7 @@ mlir::Value CIRGenFunction::emitCommonNeonBuiltinExpr(
: "aarch64.neon.sqxtn";
argTypes.push_back(builder.getExtendedOrTruncatedElementVectorType(
vTy, true /* extended */,
mlir::cast<cir::IntType>(vTy.getEltType()).isSigned()));
mlir::cast<cir::IntType>(vTy.getElementType()).isSigned()));
break;
}

Expand Down Expand Up @@ -3965,7 +3966,7 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned BuiltinID, const CallExpr *E,
case NEON::BI__builtin_neon_vbsl_v:
case NEON::BI__builtin_neon_vbslq_v: {
cir::VectorType bitTy = vTy;
if (cir::isAnyFloatingPointType(bitTy.getEltType()))
if (cir::isAnyFloatingPointType(bitTy.getElementType()))
bitTy = castVecOfFPTypeToVecOfIntWithSameWidth(builder, vTy);
Ops[0] = builder.createBitcast(Ops[0], bitTy);
Ops[1] = builder.createBitcast(Ops[1], bitTy);
Expand Down Expand Up @@ -4086,7 +4087,7 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned BuiltinID, const CallExpr *E,
builder,
{builder.getExtendedOrTruncatedElementVectorType(
vTy, true /* extend */,
mlir::cast<cir::IntType>(vTy.getEltType()).isSigned()),
mlir::cast<cir::IntType>(vTy.getElementType()).isSigned()),
SInt32Ty},
Ops, usgn ? "aarch64.neon.uqshrn" : "aarch64.neon.sqshrn", ty,
getLoc(E->getExprLoc()));
Expand All @@ -4095,15 +4096,15 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned BuiltinID, const CallExpr *E,
builder,
{builder.getExtendedOrTruncatedElementVectorType(
vTy, true /* extend */,
mlir::cast<cir::IntType>(vTy.getEltType()).isSigned()),
mlir::cast<cir::IntType>(vTy.getElementType()).isSigned()),
SInt32Ty},
Ops, "aarch64.neon.rshrn", ty, getLoc(E->getExprLoc()));
case NEON::BI__builtin_neon_vqrshrn_n_v:
return emitNeonCall(
builder,
{builder.getExtendedOrTruncatedElementVectorType(
vTy, true /* extend */,
mlir::cast<cir::IntType>(vTy.getEltType()).isSigned()),
mlir::cast<cir::IntType>(vTy.getElementType()).isSigned()),
SInt32Ty},
Ops, usgn ? "aarch64.neon.uqrshrn" : "aarch64.neon.sqrshrn", ty,
getLoc(E->getExprLoc()));
Expand Down Expand Up @@ -4469,23 +4470,23 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned BuiltinID, const CallExpr *E,
case NEON::BI__builtin_neon_vld1_lane_v:
case NEON::BI__builtin_neon_vld1q_lane_v: {
Ops[1] = builder.createBitcast(Ops[1], vTy);
Ops[0] = builder.createAlignedLoad(Ops[0].getLoc(), vTy.getEltType(),
Ops[0] = builder.createAlignedLoad(Ops[0].getLoc(), vTy.getElementType(),
Ops[0], PtrOp0.getAlignment());
return builder.create<cir::VecInsertOp>(getLoc(E->getExprLoc()), Ops[1],
Ops[0], Ops[2]);
}
case NEON::BI__builtin_neon_vldap1_lane_s64:
case NEON::BI__builtin_neon_vldap1q_lane_s64: {
cir::LoadOp Load = builder.createAlignedLoad(
Ops[0].getLoc(), vTy.getEltType(), Ops[0], PtrOp0.getAlignment());
Ops[0].getLoc(), vTy.getElementType(), Ops[0], PtrOp0.getAlignment());
Load.setAtomic(cir::MemOrder::Acquire);
return builder.create<cir::VecInsertOp>(getLoc(E->getExprLoc()),
builder.createBitcast(Ops[1], vTy),
Load, Ops[2]);
}
case NEON::BI__builtin_neon_vld1_dup_v:
case NEON::BI__builtin_neon_vld1q_dup_v: {
Address ptrAddr = PtrOp0.withElementType(builder, vTy.getEltType());
Address ptrAddr = PtrOp0.withElementType(builder, vTy.getElementType());
mlir::Value val = builder.createLoad(getLoc(E->getExprLoc()), ptrAddr);
cir::VecSplatOp vecSplat =
builder.create<cir::VecSplatOp>(getLoc(E->getExprLoc()), vTy, val);
Expand Down
2 changes: 1 addition & 1 deletion clang/lib/CIR/CodeGen/CIRGenClass.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1851,7 +1851,7 @@ void CIRGenFunction::emitCXXAggrConstructorCall(

auto arrayTy = mlir::dyn_cast<cir::ArrayType>(arrayBase.getElementType());
assert(arrayTy && "expected array type");
auto elementType = arrayTy.getEltType();
auto elementType = arrayTy.getElementType();
auto ptrToElmType = builder.getPointerTo(elementType);

// Tradional LLVM codegen emits a loop here.
Expand Down
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