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[InstCombine] Enable FoldOpIntoSelect and foldOpIntoPhi when the Op's other parameter is non-const (#166102)
This patch enables `FoldOpIntoSelect` and `foldOpIntoPhi` for the cases when Op's second parameter is a non-constant. It doesn't seem to bring significant improvements, but the compile time impact is neglegable.
1 parent 5b5d0a8 commit 628d53a

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10 files changed

+424
-73
lines changed

10 files changed

+424
-73
lines changed

‎llvm/lib/Transforms/InstCombine/InstructionCombining.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2261,11 +2261,11 @@ Instruction *InstCombinerImpl::foldBinopWithPhiOperands(BinaryOperator &BO) {
22612261
}
22622262

22632263
Instruction *InstCombinerImpl::foldBinOpIntoSelectOrPhi(BinaryOperator &I) {
2264-
if (!isa<Constant>(I.getOperand(1)))
2265-
return nullptr;
2264+
bool IsOtherParamConst = isa<Constant>(I.getOperand(1));
22662265

22672266
if (auto *Sel = dyn_cast<SelectInst>(I.getOperand(0))) {
2268-
if (Instruction *NewSel = FoldOpIntoSelect(I, Sel))
2267+
if (Instruction *NewSel =
2268+
FoldOpIntoSelect(I, Sel, false, !IsOtherParamConst))
22692269
return NewSel;
22702270
} else if (auto *PN = dyn_cast<PHINode>(I.getOperand(0))) {
22712271
if (Instruction *NewPhi = foldOpIntoPhi(I, PN))

‎llvm/test/Transforms/InstCombine/binop-phi-operands.ll‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -653,12 +653,11 @@ define i8 @mul_const_incoming0_speculatable(i1 %b, i8 %x, i8 %y) {
653653
; CHECK-NEXT: entry:
654654
; CHECK-NEXT: br i1 [[B:%.*]], label [[IF:%.*]], label [[THEN:%.*]]
655655
; CHECK: if:
656+
; CHECK-NEXT: [[TMP0:%.*]] = mul i8 [[X:%.*]], [[Y:%.*]]
656657
; CHECK-NEXT: br label [[THEN]]
657658
; CHECK: then:
658-
; CHECK-NEXT: [[P0:%.*]] = phi i8 [ 42, [[ENTRY:%.*]] ], [ [[X:%.*]], [[IF]] ]
659-
; CHECK-NEXT: [[P1:%.*]] = phi i8 [ 17, [[ENTRY]] ], [ [[Y:%.*]], [[IF]] ]
659+
; CHECK-NEXT: [[R:%.*]] = phi i8 [ -54, [[ENTRY:%.*]] ], [ [[TMP0]], [[IF]] ]
660660
; CHECK-NEXT: call void @sideeffect()
661-
; CHECK-NEXT: [[R:%.*]] = mul i8 [[P0]], [[P1]]
662661
; CHECK-NEXT: ret i8 [[R]]
663662
;
664663
entry:

‎llvm/test/Transforms/InstCombine/binop-select.ll‎

Lines changed: 186 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -335,7 +335,7 @@ define i32 @sub_sel_op1_use(i1 %b) {
335335

336336
define float @fadd_sel_op0(i1 %b, float %x) {
337337
; CHECK-LABEL: @fadd_sel_op0(
338-
; CHECK-NEXT: [[R:%.*]] = select nnan i1 [[B:%.*]], float 0xFFF0000000000000, float 0x7FF0000000000000
338+
; CHECK-NEXT: [[R:%.*]] = select i1 [[B:%.*]], float 0xFFF0000000000000, float 0x7FF0000000000000
339339
; CHECK-NEXT: ret float [[R]]
340340
;
341341
%s = select i1 %b, float 0xFFF0000000000000, float 0x7FF0000000000000
@@ -403,3 +403,188 @@ define i32 @ashr_sel_op1_use(i1 %b) {
403403
%r = ashr i32 -2, %s
404404
ret i32 %r
405405
}
406+
407+
define i8 @commonArgWithOr0(i1 %arg0) {
408+
; CHECK-LABEL: @commonArgWithOr0(
409+
; CHECK-NEXT: [[V0:%.*]] = zext i1 [[ARG0:%.*]] to i8
410+
; CHECK-NEXT: [[V1:%.*]] = select i1 [[ARG0]], i8 0, i8 8
411+
; CHECK-NEXT: [[V2:%.*]] = or disjoint i8 [[V1]], [[V0]]
412+
; CHECK-NEXT: [[V3:%.*]] = or disjoint i8 [[V2]], 16
413+
; CHECK-NEXT: ret i8 [[V3]]
414+
;
415+
%v0 = zext i1 %arg0 to i8
416+
%v1 = select i1 %arg0, i8 0, i8 8
417+
%v2 = or i8 %v1, %v0
418+
%v3 = or i8 %v2, 16
419+
ret i8 %v3
420+
}
421+
422+
define i8 @commonArgWithOr1(i1 %arg0) {
423+
; CHECK-LABEL: @commonArgWithOr1(
424+
; CHECK-NEXT: [[V3:%.*]] = select i1 [[ARG0:%.*]], i8 17, i8 23
425+
; CHECK-NEXT: ret i8 [[V3]]
426+
;
427+
%v0 = zext i1 %arg0 to i8
428+
%v1 = select i1 %arg0, i8 1, i8 7
429+
%v2 = or i8 %v1, %v0
430+
%v3 = or i8 %v2, 16
431+
ret i8 %v3
432+
}
433+
434+
define i8 @commonArgWithOr2(i1 %arg0) {
435+
; CHECK-LABEL: @commonArgWithOr2(
436+
; CHECK-NEXT: [[V0:%.*]] = zext i1 [[ARG0:%.*]] to i8
437+
; CHECK-NEXT: [[V1:%.*]] = select i1 [[ARG0]], i8 5, i8 42
438+
; CHECK-NEXT: [[V2:%.*]] = or i8 [[V1]], [[V0]]
439+
; CHECK-NEXT: [[V3:%.*]] = or disjoint i8 [[V2]], 16
440+
; CHECK-NEXT: ret i8 [[V3]]
441+
;
442+
%v0 = zext i1 %arg0 to i8
443+
%v1 = select i1 %arg0, i8 21, i8 42
444+
%v2 = or i8 %v1, %v0
445+
%v3 = or i8 %v2, 16
446+
ret i8 %v3
447+
}
448+
449+
define i8 @commonArgWithAnd0(i1 %arg0) {
450+
; CHECK-LABEL: @commonArgWithAnd0(
451+
; CHECK-NEXT: ret i8 16
452+
;
453+
%v0 = zext i1 %arg0 to i8
454+
%v1 = select i1 %arg0, i8 0, i8 8
455+
%v2 = and i8 %v1, %v0
456+
%v3 = or i8 %v2, 16
457+
ret i8 %v3
458+
}
459+
460+
define i8 @commonArgWithAnd1(i1 %arg0) {
461+
; CHECK-LABEL: @commonArgWithAnd1(
462+
; CHECK-NEXT: ret i8 16
463+
;
464+
%v0 = zext i1 %arg0 to i8
465+
%v1 = select i1 %arg0, i8 8, i8 1
466+
%v2 = and i8 %v1, %v0
467+
%v3 = or i8 %v2, 16
468+
ret i8 %v3
469+
}
470+
471+
define i8 @commonArgWithAnd2(i1 %arg0) {
472+
; CHECK-LABEL: @commonArgWithAnd2(
473+
; CHECK-NEXT: [[V2:%.*]] = zext i1 [[ARG0:%.*]] to i8
474+
; CHECK-NEXT: [[V3:%.*]] = or disjoint i8 [[V2]], 16
475+
; CHECK-NEXT: ret i8 [[V3]]
476+
;
477+
%v0 = zext i1 %arg0 to i8
478+
%v1 = select i1 %arg0, i8 1, i8 7
479+
%v2 = and i8 %v1, %v0
480+
%v3 = or i8 %v2, 16
481+
ret i8 %v3
482+
}
483+
484+
define i8 @commonArgWithAnd3(i1 %arg0) {
485+
; CHECK-LABEL: @commonArgWithAnd3(
486+
; CHECK-NEXT: [[V2:%.*]] = zext i1 [[ARG0:%.*]] to i8
487+
; CHECK-NEXT: [[V3:%.*]] = or disjoint i8 [[V2]], 16
488+
; CHECK-NEXT: ret i8 [[V3]]
489+
;
490+
%v0 = zext i1 %arg0 to i8
491+
%v1 = select i1 %arg0, i8 21, i8 42
492+
%v2 = and i8 %v1, %v0
493+
%v3 = or i8 %v2, 16
494+
ret i8 %v3
495+
}
496+
497+
define i8 @commonArgWithXor0(i1 %arg0) {
498+
; CHECK-LABEL: @commonArgWithXor0(
499+
; CHECK-NEXT: [[V0:%.*]] = zext i1 [[ARG0:%.*]] to i8
500+
; CHECK-NEXT: [[V1:%.*]] = select i1 [[ARG0]], i8 0, i8 8
501+
; CHECK-NEXT: [[V2:%.*]] = or disjoint i8 [[V1]], [[V0]]
502+
; CHECK-NEXT: [[V3:%.*]] = or disjoint i8 [[V2]], 16
503+
; CHECK-NEXT: ret i8 [[V3]]
504+
;
505+
%v0 = zext i1 %arg0 to i8
506+
%v1 = select i1 %arg0, i8 0, i8 8
507+
%v2 = xor i8 %v1, %v0
508+
%v3 = or i8 %v2, 16
509+
ret i8 %v3
510+
}
511+
512+
define i8 @commonArgWithXor1(i1 %arg0) {
513+
; CHECK-LABEL: @commonArgWithXor1(
514+
; CHECK-NEXT: [[V0:%.*]] = zext i1 [[ARG0:%.*]] to i8
515+
; CHECK-NEXT: [[V1:%.*]] = select i1 [[ARG0]], i8 9, i8 1
516+
; CHECK-NEXT: [[V2:%.*]] = xor i8 [[V1]], [[V0]]
517+
; CHECK-NEXT: ret i8 [[V2]]
518+
;
519+
%v0 = zext i1 %arg0 to i8
520+
%v1 = select i1 %arg0, i8 9, i8 1
521+
%v2 = xor i8 %v1, %v0
522+
ret i8 %v2
523+
}
524+
525+
define i8 @commonArgWithXor2(i1 %arg0) {
526+
; CHECK-LABEL: @commonArgWithXor2(
527+
; CHECK-NEXT: [[V0:%.*]] = zext i1 [[ARG0:%.*]] to i8
528+
; CHECK-NEXT: [[V1:%.*]] = select i1 [[ARG0]], i8 1, i8 7
529+
; CHECK-NEXT: [[V2:%.*]] = xor i8 [[V1]], [[V0]]
530+
; CHECK-NEXT: [[V3:%.*]] = or disjoint i8 [[V2]], 16
531+
; CHECK-NEXT: ret i8 [[V3]]
532+
;
533+
%v0 = zext i1 %arg0 to i8
534+
%v1 = select i1 %arg0, i8 1, i8 7
535+
%v2 = xor i8 %v1, %v0
536+
%v3 = or i8 %v2, 16
537+
ret i8 %v3
538+
}
539+
540+
define i8 @commonArgWithXor3(i1 %arg0) {
541+
; CHECK-LABEL: @commonArgWithXor3(
542+
; CHECK-NEXT: [[V0:%.*]] = zext i1 [[ARG0:%.*]] to i8
543+
; CHECK-NEXT: [[V1:%.*]] = select i1 [[ARG0]], i8 5, i8 45
544+
; CHECK-NEXT: [[V2:%.*]] = xor i8 [[V1]], [[V0]]
545+
; CHECK-NEXT: [[V3:%.*]] = or disjoint i8 [[V2]], 16
546+
; CHECK-NEXT: ret i8 [[V3]]
547+
;
548+
%v0 = zext i1 %arg0 to i8
549+
%v1 = select i1 %arg0, i8 21, i8 45
550+
%v2 = xor i8 %v1, %v0
551+
%v3 = or i8 %v2, 16
552+
ret i8 %v3
553+
}
554+
555+
define i8 @commonArgWithAdd0(i1 %arg0) {
556+
; CHECK-LABEL: @commonArgWithAdd0(
557+
; CHECK-NEXT: [[V3:%.*]] = select i1 [[ARG0:%.*]], i8 22, i8 61
558+
; CHECK-NEXT: ret i8 [[V3]]
559+
;
560+
%v0 = zext i1 %arg0 to i8
561+
%v1 = select i1 %arg0, i8 21, i8 45
562+
%v2 = add i8 %v1, %v0
563+
%v3 = or i8 %v2, 16
564+
ret i8 %v3
565+
}
566+
567+
define i32 @OrSelectIcmpZero(i32 %a, i32 %b) {
568+
; CHECK-LABEL: @OrSelectIcmpZero(
569+
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], 0
570+
; CHECK-NEXT: [[OR:%.*]] = select i1 [[CMP]], i32 [[B:%.*]], i32 [[A]]
571+
; CHECK-NEXT: ret i32 [[OR]]
572+
;
573+
%cmp = icmp eq i32 %a, 0
574+
%sel = select i1 %cmp, i32 %b, i32 0
575+
%or = or i32 %sel, %a
576+
ret i32 %or
577+
}
578+
579+
define i32 @OrSelectIcmpNonZero(i32 %a, i32 %b) {
580+
; CHECK-LABEL: @OrSelectIcmpNonZero(
581+
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], 0
582+
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 [[B:%.*]], i32 42
583+
; CHECK-NEXT: [[OR:%.*]] = or i32 [[SEL]], [[A]]
584+
; CHECK-NEXT: ret i32 [[OR]]
585+
;
586+
%cmp = icmp eq i32 %a, 0
587+
%sel = select i1 %cmp, i32 %b, i32 42
588+
%or = or i32 %sel, %a
589+
ret i32 %or
590+
}

‎llvm/test/Transforms/InstCombine/dont-distribute-phi.ll‎

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
77
define zeroext i1 @foo(i32 %arg) {
88
; CHECK-LABEL: @foo(
99
; CHECK-NEXT: entry:
10-
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[ARG:%.*]], 37
10+
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[ARG:%.*]], 37
1111
; CHECK-NEXT: br i1 [[CMP1]], label [[BB_ELSE:%.*]], label [[BB_THEN:%.*]]
1212
; CHECK: bb_then:
1313
; CHECK-NEXT: call void @bar()
@@ -16,8 +16,7 @@ define zeroext i1 @foo(i32 %arg) {
1616
; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 [[ARG]], 17
1717
; CHECK-NEXT: br label [[BB_EXIT]]
1818
; CHECK: bb_exit:
19-
; CHECK-NEXT: [[PHI1:%.*]] = phi i1 [ [[CMP2]], [[BB_ELSE]] ], [ undef, [[BB_THEN]] ]
20-
; CHECK-NEXT: [[AND1:%.*]] = and i1 [[PHI1]], [[CMP1]]
19+
; CHECK-NEXT: [[AND1:%.*]] = phi i1 [ [[CMP2]], [[BB_THEN]] ], [ false, [[BB_ELSE]] ]
2120
; CHECK-NEXT: ret i1 [[AND1]]
2221
;
2322

@@ -43,7 +42,7 @@ bb_exit:
4342
define zeroext i1 @foo_logical(i32 %arg) {
4443
; CHECK-LABEL: @foo_logical(
4544
; CHECK-NEXT: entry:
46-
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[ARG:%.*]], 37
45+
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[ARG:%.*]], 37
4746
; CHECK-NEXT: br i1 [[CMP1]], label [[BB_ELSE:%.*]], label [[BB_THEN:%.*]]
4847
; CHECK: bb_then:
4948
; CHECK-NEXT: call void @bar()
@@ -52,8 +51,7 @@ define zeroext i1 @foo_logical(i32 %arg) {
5251
; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 [[ARG]], 17
5352
; CHECK-NEXT: br label [[BB_EXIT]]
5453
; CHECK: bb_exit:
55-
; CHECK-NEXT: [[PHI1:%.*]] = phi i1 [ [[CMP2]], [[BB_ELSE]] ], [ undef, [[BB_THEN]] ]
56-
; CHECK-NEXT: [[AND1:%.*]] = and i1 [[PHI1]], [[CMP1]]
54+
; CHECK-NEXT: [[AND1:%.*]] = phi i1 [ [[CMP2]], [[BB_THEN]] ], [ false, [[BB_ELSE]] ]
5755
; CHECK-NEXT: ret i1 [[AND1]]
5856
;
5957

‎llvm/test/Transforms/InstCombine/fmul.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1222,7 +1222,7 @@ define <2 x double> @negate_if_true_wrong_constant(<2 x double> %px, i1 %cond) {
12221222
; X *fast (C ? 1.0 : 0.0) -> C ? X : 0.0
12231223
define float @fmul_select(float %x, i1 %c) {
12241224
; CHECK-LABEL: @fmul_select(
1225-
; CHECK-NEXT: [[MUL:%.*]] = select fast i1 [[C:%.*]], float [[X:%.*]], float 0.000000e+00
1225+
; CHECK-NEXT: [[MUL:%.*]] = select i1 [[C:%.*]], float [[X:%.*]], float 0.000000e+00
12261226
; CHECK-NEXT: ret float [[MUL]]
12271227
;
12281228
%sel = select i1 %c, float 1.0, float 0.0
@@ -1233,7 +1233,7 @@ define float @fmul_select(float %x, i1 %c) {
12331233
; X *fast (C ? 1.0 : 0.0) -> C ? X : 0.0
12341234
define <2 x float> @fmul_select_vec(<2 x float> %x, i1 %c) {
12351235
; CHECK-LABEL: @fmul_select_vec(
1236-
; CHECK-NEXT: [[MUL:%.*]] = select fast i1 [[C:%.*]], <2 x float> [[X:%.*]], <2 x float> zeroinitializer
1236+
; CHECK-NEXT: [[MUL:%.*]] = select i1 [[C:%.*]], <2 x float> [[X:%.*]], <2 x float> zeroinitializer
12371237
; CHECK-NEXT: ret <2 x float> [[MUL]]
12381238
;
12391239
%sel = select i1 %c, <2 x float> <float 1.0, float 1.0>, <2 x float> zeroinitializer

‎llvm/test/Transforms/InstCombine/free-inversion.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -563,10 +563,10 @@ define i1 @test_inv_free(i1 %c1, i1 %c2, i1 %c3, i1 %c4) {
563563
; CHECK: b2:
564564
; CHECK-NEXT: br label [[EXIT]]
565565
; CHECK: b3:
566+
; CHECK-NEXT: [[TMP0:%.*]] = and i1 [[C3:%.*]], [[C4:%.*]]
566567
; CHECK-NEXT: br label [[EXIT]]
567568
; CHECK: exit:
568-
; CHECK-NEXT: [[VAL_NOT:%.*]] = phi i1 [ false, [[B1]] ], [ true, [[B2]] ], [ [[C3:%.*]], [[B3]] ]
569-
; CHECK-NEXT: [[COND_NOT:%.*]] = and i1 [[VAL_NOT]], [[C4:%.*]]
569+
; CHECK-NEXT: [[COND_NOT:%.*]] = phi i1 [ false, [[B1]] ], [ [[C4]], [[B2]] ], [ [[TMP0]], [[B3]] ]
570570
; CHECK-NEXT: br i1 [[COND_NOT]], label [[B5:%.*]], label [[B4:%.*]]
571571
; CHECK: b4:
572572
; CHECK-NEXT: ret i1 true

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