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[RISCV] Add ADD to getRegAllocationHints to improve to improve use of c.add.
add can always be compressed to c.add if one of the sources is the same as the destination. The same is not true for c.addw where the registers need to be x8-x15.
1 parent e4aad51 commit 64612f5

21 files changed

+196
-195
lines changed

‎llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -419,6 +419,7 @@ bool RISCVRegisterInfo::getRegAllocationHints(
419419
switch (MI.getOpcode()) {
420420
default:
421421
return false;
422+
case RISCV::ADD:
422423
case RISCV::SLLI:
423424
return true;
424425
case RISCV::ADDI:

‎llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -335,8 +335,8 @@ define i64 @callee_aligned_stack(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i128 %f
335335
; RV64I-NEXT: ld a1, 0(sp)
336336
; RV64I-NEXT: ld a2, 16(sp)
337337
; RV64I-NEXT: ld a3, 32(sp)
338-
; RV64I-NEXT: add a4, a5, a7
339-
; RV64I-NEXT: add a1, a4, a1
338+
; RV64I-NEXT: add a5, a5, a7
339+
; RV64I-NEXT: add a1, a5, a1
340340
; RV64I-NEXT: add a1, a1, a2
341341
; RV64I-NEXT: add a1, a1, a3
342342
; RV64I-NEXT: add a0, a1, a0

‎llvm/test/CodeGen/RISCV/div-by-constant.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -83,8 +83,8 @@ define i64 @udiv64_constant_no_add(i64 %a) nounwind {
8383
; RV32-NEXT: add a3, a6, a3
8484
; RV32-NEXT: sltu a0, a0, a2
8585
; RV32-NEXT: sub a0, a1, a0
86-
; RV32-NEXT: mul a0, a0, a4
87-
; RV32-NEXT: add a1, a3, a0
86+
; RV32-NEXT: mul a1, a0, a4
87+
; RV32-NEXT: add a1, a3, a1
8888
; RV32-NEXT: mul a0, a5, a4
8989
; RV32-NEXT: ret
9090
;

‎llvm/test/CodeGen/RISCV/div-pow2.ll‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -408,9 +408,9 @@ define i64 @sdiv64_pow2_8589934592(i64 %a) {
408408
; RV32I-NEXT: srai a1, a1, 31
409409
; RV32I-NEXT: add a1, a0, a1
410410
; RV32I-NEXT: sltu a0, a1, a0
411-
; RV32I-NEXT: add a1, a2, a0
412-
; RV32I-NEXT: srai a0, a1, 1
413-
; RV32I-NEXT: srai a1, a1, 31
411+
; RV32I-NEXT: add a2, a2, a0
412+
; RV32I-NEXT: srai a0, a2, 1
413+
; RV32I-NEXT: srai a1, a2, 31
414414
; RV32I-NEXT: ret
415415
;
416416
; RV64I-LABEL: sdiv64_pow2_8589934592:

‎llvm/test/CodeGen/RISCV/div.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -198,8 +198,8 @@ define i64 @udiv64_constant(i64 %a) nounwind {
198198
; RV32IM-NEXT: add a3, a6, a3
199199
; RV32IM-NEXT: sltu a0, a0, a2
200200
; RV32IM-NEXT: sub a0, a1, a0
201-
; RV32IM-NEXT: mul a0, a0, a4
202-
; RV32IM-NEXT: add a1, a3, a0
201+
; RV32IM-NEXT: mul a1, a0, a4
202+
; RV32IM-NEXT: add a1, a3, a1
203203
; RV32IM-NEXT: mul a0, a5, a4
204204
; RV32IM-NEXT: ret
205205
;

‎llvm/test/CodeGen/RISCV/mul.ll‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1412,8 +1412,8 @@ define i64 @mulhsu_i64(i64 %a, i64 %b) nounwind {
14121412
; RV32I-NEXT: mv a2, s2
14131413
; RV32I-NEXT: li a3, 0
14141414
; RV32I-NEXT: call __muldi3@plt
1415-
; RV32I-NEXT: add a2, a0, s5
1416-
; RV32I-NEXT: sltu a0, a2, a0
1415+
; RV32I-NEXT: add s5, a0, s5
1416+
; RV32I-NEXT: sltu a0, s5, a0
14171417
; RV32I-NEXT: add a0, a1, a0
14181418
; RV32I-NEXT: add s8, s7, a0
14191419
; RV32I-NEXT: mv a0, s0
@@ -1436,18 +1436,18 @@ define i64 @mulhsu_i64(i64 %a, i64 %b) nounwind {
14361436
; RV32I-NEXT: mv a2, s1
14371437
; RV32I-NEXT: mv a3, s0
14381438
; RV32I-NEXT: call __muldi3@plt
1439-
; RV32I-NEXT: add a3, a0, s2
1440-
; RV32I-NEXT: add a2, s9, a3
1441-
; RV32I-NEXT: sltu a4, a2, s9
1442-
; RV32I-NEXT: sltu a5, s9, s5
1443-
; RV32I-NEXT: sltu a6, s8, s7
1444-
; RV32I-NEXT: add a6, s6, a6
1445-
; RV32I-NEXT: add a5, a6, a5
1439+
; RV32I-NEXT: add s2, a0, s2
1440+
; RV32I-NEXT: add a2, s9, s2
1441+
; RV32I-NEXT: sltu a3, a2, s9
1442+
; RV32I-NEXT: sltu a4, s9, s5
1443+
; RV32I-NEXT: sltu a5, s8, s7
1444+
; RV32I-NEXT: add a5, s6, a5
1445+
; RV32I-NEXT: add a4, a5, a4
14461446
; RV32I-NEXT: add a1, a1, s3
1447-
; RV32I-NEXT: sltu a0, a3, a0
1447+
; RV32I-NEXT: sltu a0, s2, a0
14481448
; RV32I-NEXT: add a0, a1, a0
1449-
; RV32I-NEXT: add a0, a5, a0
1450-
; RV32I-NEXT: add a1, a0, a4
1449+
; RV32I-NEXT: add a0, a4, a0
1450+
; RV32I-NEXT: add a1, a0, a3
14511451
; RV32I-NEXT: mv a0, a2
14521452
; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
14531453
; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload

‎llvm/test/CodeGen/RISCV/rotl-rotr.ll‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1076,8 +1076,8 @@ define signext i64 @rotl_64_mask_shared(i64 signext %a, i64 signext %b, i64 sign
10761076
; RV32I-NEXT: and a0, a0, a2
10771077
; RV32I-NEXT: add a0, a1, a0
10781078
; RV32I-NEXT: sltu a1, a0, a1
1079-
; RV32I-NEXT: add a2, a5, a3
1080-
; RV32I-NEXT: add a1, a2, a1
1079+
; RV32I-NEXT: add a3, a5, a3
1080+
; RV32I-NEXT: add a1, a3, a1
10811081
; RV32I-NEXT: ret
10821082
;
10831083
; RV64I-LABEL: rotl_64_mask_shared:
@@ -1131,8 +1131,8 @@ define signext i64 @rotl_64_mask_shared(i64 signext %a, i64 signext %b, i64 sign
11311131
; RV32ZBB-NEXT: and a0, a0, a2
11321132
; RV32ZBB-NEXT: add a0, a1, a0
11331133
; RV32ZBB-NEXT: sltu a1, a0, a1
1134-
; RV32ZBB-NEXT: add a2, a5, a3
1135-
; RV32ZBB-NEXT: add a1, a2, a1
1134+
; RV32ZBB-NEXT: add a3, a5, a3
1135+
; RV32ZBB-NEXT: add a1, a3, a1
11361136
; RV32ZBB-NEXT: ret
11371137
;
11381138
; RV64ZBB-LABEL: rotl_64_mask_shared:
@@ -1549,10 +1549,10 @@ define i64 @rotr_64_mask_multiple(i64 %a, i64 %b, i64 %amt) nounwind {
15491549
; RV32I-NEXT: slli a6, a6, 1
15501550
; RV32I-NEXT: sll a0, a6, a0
15511551
; RV32I-NEXT: or a0, a0, a3
1552-
; RV32I-NEXT: add a3, a7, a0
1552+
; RV32I-NEXT: add a7, a7, a0
15531553
; RV32I-NEXT: add a0, a1, a2
15541554
; RV32I-NEXT: sltu a1, a0, a1
1555-
; RV32I-NEXT: add a1, a3, a1
1555+
; RV32I-NEXT: add a1, a7, a1
15561556
; RV32I-NEXT: ret
15571557
;
15581558
; RV64I-LABEL: rotr_64_mask_multiple:
@@ -1605,10 +1605,10 @@ define i64 @rotr_64_mask_multiple(i64 %a, i64 %b, i64 %amt) nounwind {
16051605
; RV32ZBB-NEXT: slli a6, a6, 1
16061606
; RV32ZBB-NEXT: sll a0, a6, a0
16071607
; RV32ZBB-NEXT: or a0, a0, a3
1608-
; RV32ZBB-NEXT: add a3, a7, a0
1608+
; RV32ZBB-NEXT: add a7, a7, a0
16091609
; RV32ZBB-NEXT: add a0, a1, a2
16101610
; RV32ZBB-NEXT: sltu a1, a0, a1
1611-
; RV32ZBB-NEXT: add a1, a3, a1
1611+
; RV32ZBB-NEXT: add a1, a7, a1
16121612
; RV32ZBB-NEXT: ret
16131613
;
16141614
; RV64ZBB-LABEL: rotr_64_mask_multiple:

‎llvm/test/CodeGen/RISCV/rv32zba.ll‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -44,9 +44,9 @@ define i64 @sh3add(i64 %0, i64* %1) {
4444
; RV32I-LABEL: sh3add:
4545
; RV32I: # %bb.0:
4646
; RV32I-NEXT: slli a0, a0, 3
47-
; RV32I-NEXT: add a1, a2, a0
48-
; RV32I-NEXT: lw a0, 0(a1)
49-
; RV32I-NEXT: lw a1, 4(a1)
47+
; RV32I-NEXT: add a2, a2, a0
48+
; RV32I-NEXT: lw a0, 0(a2)
49+
; RV32I-NEXT: lw a1, 4(a2)
5050
; RV32I-NEXT: ret
5151
;
5252
; RV32ZBA-LABEL: sh3add:

‎llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll‎

Lines changed: 28 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -82,10 +82,10 @@ define fastcc <vscale x 64 x i32> @ret_split_nxv64i32(<vscale x 64 x i32>* %x) {
8282
; CHECK-NEXT: vl8re32.v v24, (a1)
8383
; CHECK-NEXT: vl8re32.v v0, (a5)
8484
; CHECK-NEXT: vs8r.v v16, (a0)
85-
; CHECK-NEXT: add a1, a0, a2
86-
; CHECK-NEXT: vs8r.v v24, (a1)
87-
; CHECK-NEXT: add a1, a0, a4
88-
; CHECK-NEXT: vs8r.v v0, (a1)
85+
; CHECK-NEXT: add a2, a0, a2
86+
; CHECK-NEXT: vs8r.v v24, (a2)
87+
; CHECK-NEXT: add a4, a0, a4
88+
; CHECK-NEXT: vs8r.v v0, (a4)
8989
; CHECK-NEXT: add a0, a0, a3
9090
; CHECK-NEXT: vs8r.v v8, (a0)
9191
; CHECK-NEXT: ret
@@ -148,30 +148,30 @@ define fastcc <vscale x 128 x i32> @ret_split_nxv128i32(<vscale x 128 x i32>* %x
148148
; CHECK-NEXT: vl8re32.v v16, (t3)
149149
; CHECK-NEXT: vl8re32.v v24, (t2)
150150
; CHECK-NEXT: vs8r.v v8, (a0)
151-
; CHECK-NEXT: add a1, a0, a2
152-
; CHECK-NEXT: vs8r.v v16, (a1)
153-
; CHECK-NEXT: add a1, a0, t1
154-
; CHECK-NEXT: vs8r.v v24, (a1)
155-
; CHECK-NEXT: add a1, a0, a7
156-
; CHECK-NEXT: vs8r.v v0, (a1)
157-
; CHECK-NEXT: add a1, a0, a6
158-
; CHECK-NEXT: addi a2, sp, 16
159-
; CHECK-NEXT: vl8re8.v v8, (a2) # Unknown-size Folded Reload
160-
; CHECK-NEXT: vs8r.v v8, (a1)
161-
; CHECK-NEXT: add a1, a0, a5
162-
; CHECK-NEXT: csrr a2, vlenb
163-
; CHECK-NEXT: slli a2, a2, 3
164-
; CHECK-NEXT: add a2, sp, a2
165-
; CHECK-NEXT: addi a2, a2, 16
166-
; CHECK-NEXT: vl8re8.v v8, (a2) # Unknown-size Folded Reload
167-
; CHECK-NEXT: vs8r.v v8, (a1)
168-
; CHECK-NEXT: add a1, a0, a4
169-
; CHECK-NEXT: csrr a2, vlenb
170-
; CHECK-NEXT: slli a2, a2, 4
171-
; CHECK-NEXT: add a2, sp, a2
172-
; CHECK-NEXT: addi a2, a2, 16
173-
; CHECK-NEXT: vl8re8.v v8, (a2) # Unknown-size Folded Reload
174-
; CHECK-NEXT: vs8r.v v8, (a1)
151+
; CHECK-NEXT: add a2, a0, a2
152+
; CHECK-NEXT: vs8r.v v16, (a2)
153+
; CHECK-NEXT: add t1, a0, t1
154+
; CHECK-NEXT: vs8r.v v24, (t1)
155+
; CHECK-NEXT: add a7, a0, a7
156+
; CHECK-NEXT: vs8r.v v0, (a7)
157+
; CHECK-NEXT: add a6, a0, a6
158+
; CHECK-NEXT: addi a1, sp, 16
159+
; CHECK-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload
160+
; CHECK-NEXT: vs8r.v v8, (a6)
161+
; CHECK-NEXT: add a5, a0, a5
162+
; CHECK-NEXT: csrr a1, vlenb
163+
; CHECK-NEXT: slli a1, a1, 3
164+
; CHECK-NEXT: add a1, sp, a1
165+
; CHECK-NEXT: addi a1, a1, 16
166+
; CHECK-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload
167+
; CHECK-NEXT: vs8r.v v8, (a5)
168+
; CHECK-NEXT: add a4, a0, a4
169+
; CHECK-NEXT: csrr a1, vlenb
170+
; CHECK-NEXT: slli a1, a1, 4
171+
; CHECK-NEXT: add a1, sp, a1
172+
; CHECK-NEXT: addi a1, a1, 16
173+
; CHECK-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload
174+
; CHECK-NEXT: vs8r.v v8, (a4)
175175
; CHECK-NEXT: add a0, a0, a3
176176
; CHECK-NEXT: csrr a1, vlenb
177177
; CHECK-NEXT: li a2, 24

‎llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -151,18 +151,18 @@ define i1 @extractelt_nxv128i1(<vscale x 128 x i8>* %x, i64 %idx) nounwind {
151151
; RV32-NEXT: add a4, a0, a2
152152
; RV32-NEXT: vl8r.v v16, (a4)
153153
; RV32-NEXT: vl8r.v v24, (a0)
154-
; RV32-NEXT: add a0, a3, a1
155-
; RV32-NEXT: vsetvli a1, zero, e8, m8, ta, ma
154+
; RV32-NEXT: add a1, a3, a1
155+
; RV32-NEXT: vsetvli a0, zero, e8, m8, ta, ma
156156
; RV32-NEXT: vmseq.vi v8, v16, 0
157157
; RV32-NEXT: vmseq.vi v0, v24, 0
158158
; RV32-NEXT: vmv.v.i v16, 0
159159
; RV32-NEXT: vmerge.vim v24, v16, 1, v0
160160
; RV32-NEXT: vs8r.v v24, (a3)
161-
; RV32-NEXT: add a1, a3, a2
161+
; RV32-NEXT: add a2, a3, a2
162162
; RV32-NEXT: vmv1r.v v0, v8
163163
; RV32-NEXT: vmerge.vim v8, v16, 1, v0
164-
; RV32-NEXT: vs8r.v v8, (a1)
165-
; RV32-NEXT: lb a0, 0(a0)
164+
; RV32-NEXT: vs8r.v v8, (a2)
165+
; RV32-NEXT: lb a0, 0(a1)
166166
; RV32-NEXT: addi sp, s0, -80
167167
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
168168
; RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
@@ -191,18 +191,18 @@ define i1 @extractelt_nxv128i1(<vscale x 128 x i8>* %x, i64 %idx) nounwind {
191191
; RV64-NEXT: add a4, a0, a2
192192
; RV64-NEXT: vl8r.v v16, (a4)
193193
; RV64-NEXT: vl8r.v v24, (a0)
194-
; RV64-NEXT: add a0, a3, a1
195-
; RV64-NEXT: vsetvli a1, zero, e8, m8, ta, ma
194+
; RV64-NEXT: add a1, a3, a1
195+
; RV64-NEXT: vsetvli a0, zero, e8, m8, ta, ma
196196
; RV64-NEXT: vmseq.vi v8, v16, 0
197197
; RV64-NEXT: vmseq.vi v0, v24, 0
198198
; RV64-NEXT: vmv.v.i v16, 0
199199
; RV64-NEXT: vmerge.vim v24, v16, 1, v0
200200
; RV64-NEXT: vs8r.v v24, (a3)
201-
; RV64-NEXT: add a1, a3, a2
201+
; RV64-NEXT: add a2, a3, a2
202202
; RV64-NEXT: vmv1r.v v0, v8
203203
; RV64-NEXT: vmerge.vim v8, v16, 1, v0
204-
; RV64-NEXT: vs8r.v v8, (a1)
205-
; RV64-NEXT: lb a0, 0(a0)
204+
; RV64-NEXT: vs8r.v v8, (a2)
205+
; RV64-NEXT: lb a0, 0(a1)
206206
; RV64-NEXT: addi sp, s0, -80
207207
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
208208
; RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload

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