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[AArch64][llvm] Armv9.7-A: Add support for TLBI Domains (FEAT_TLBID) (#163156)
Allow the following `TLBI` operation types to take an optional register operand when enabled by `FEAT_TLBID`: - ALL* - VMALL* - VMALLS12* - VMALLWS2* as documented here: * https://developer.arm.com/documentation/ddi0602/2025-09/ * https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions Notes on implementation: Currently, AArch64 `SYS` alias instructions fall into two categories: * a register value must be present (indicated by any value except `XZR`) * no register value must be present (this value must be `XZR`) When +tblid is enabled, `SYS` aliases are now allowed to take an optional register, or no register as before. We need an extra tablegen flag to indicate if the register is optional or not (the existing "NeedsReg" flag is binary and not suitable; the register is either present or absent, not either for a specific TLBI operation) Don't produce an error message if the register operand is missing or unexpected, if it is specified as an optional register.
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‎clang/test/Driver/aarch64-v97a.c‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -25,3 +25,7 @@
2525
// RUN: %clang -target aarch64 -march=armv9.7a+lscp -### -c %s 2>&1 | FileCheck -check-prefix=V97A-LSCP %s
2626
// RUN: %clang -target aarch64 -march=armv9.7-a+lscp -### -c %s 2>&1 | FileCheck -check-prefix=V97A-LSCP %s
2727
// V97A-LSCP: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.7a"{{.*}} "-target-feature" "+lscp"
28+
29+
// RUN: %clang -target aarch64 -march=armv9.7a+tlbid -### -c %s 2>&1 | FileCheck -check-prefix=V97A-TLBID %s
30+
// RUN: %clang -target aarch64 -march=armv9.7-a+tlbid -### -c %s 2>&1 | FileCheck -check-prefix=V97A-TLBID %s
31+
// V97A-TLBID: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.7a"{{.*}} "-target-feature" "+tlbid"

‎clang/test/Driver/print-supported-extensions-aarch64.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -104,6 +104,7 @@
104104
// CHECK-NEXT: sve2p1 FEAT_SVE2p1 Enable Scalable Vector Extension 2.1 instructions
105105
// CHECK-NEXT: sve2p2 FEAT_SVE2p2 Enable Armv9.6-A Scalable Vector Extension 2.2 instructions
106106
// CHECK-NEXT: the FEAT_THE Enable Armv8.9-A Translation Hardening Extension
107+
// CHECK-NEXT: tlbid FEAT_TLBID Enable Armv9.7-A TLBI Domains extension
107108
// CHECK-NEXT: tlbiw FEAT_TLBIW Enable Armv9.5-A TLBI VMALL for Dirty State
108109
// CHECK-NEXT: tme FEAT_TME Enable Transactional Memory Extension
109110
// CHECK-NEXT: wfxt FEAT_WFxT Enable Armv8.7-A WFET and WFIT instruction

‎llvm/lib/Target/AArch64/AArch64Features.td‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -595,6 +595,9 @@ def FeatureCMH : ExtensionWithMArch<"cmh", "CMH", "FEAT_CMH",
595595
def FeatureLSCP : ExtensionWithMArch<"lscp", "LSCP", "FEAT_LSCP",
596596
"Enable Armv9.7-A Load-acquire and store-release pair extension">;
597597

598+
def FeatureTLBID: ExtensionWithMArch<"tlbid", "TLBID", "FEAT_TLBID",
599+
"Enable Armv9.7-A TLBI Domains extension">;
600+
598601
//===----------------------------------------------------------------------===//
599602
// Other Features
600603
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -400,6 +400,8 @@ def HasGCS : Predicate<"Subtarget->hasGCS()">,
400400
AssemblerPredicateWithAll<(all_of FeatureGCS), "gcs">;
401401
def HasCPA : Predicate<"Subtarget->hasCPA()">,
402402
AssemblerPredicateWithAll<(all_of FeatureCPA), "cpa">;
403+
def HasTLBID : Predicate<"Subtarget->hasTLBID()">,
404+
AssemblerPredicateWithAll<(all_of FeatureTLBID), "tlbid">;
403405
def IsLE : Predicate<"Subtarget->isLittleEndian()">;
404406
def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
405407
def IsWindows : Predicate<"Subtarget->isTargetWindows()">;

‎llvm/lib/Target/AArch64/AArch64SystemOperands.td‎

Lines changed: 37 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -832,32 +832,33 @@ def : CMHPriorityHint<"ph", 0b1>;
832832
//===----------------------------------------------------------------------===//
833833

834834
class TLBICommon<string name, bits<3> op1, bits<4> crn, bits<4> crm,
835-
bits<3> op2, bit needsreg> {
835+
bits<3> op2, bit needsreg, bit optionalreg> {
836836
string Name = name;
837837
bits<14> Encoding;
838838
let Encoding{13-11} = op1;
839839
let Encoding{10-7} = crn;
840840
let Encoding{6-3} = crm;
841841
let Encoding{2-0} = op2;
842842
bit NeedsReg = needsreg;
843+
bit OptionalReg = optionalreg;
843844
list<string> Requires = [];
844845
list<string> ExtraRequires = [];
845846
code RequiresStr = [{ { }] # !interleave(Requires # ExtraRequires, [{, }]) # [{ } }];
846847
}
847848

848849
class TLBIEntry<string name, bits<3> op1, bits<4> crn, bits<4> crm,
849-
bits<3> op2, bit needsreg>
850-
: TLBICommon<name, op1, crn, crm, op2, needsreg>;
850+
bits<3> op2, bit needsreg, bit optionalreg>
851+
: TLBICommon<name, op1, crn, crm, op2, needsreg, optionalreg>;
851852

852853
class TLBIPEntry<string name, bits<3> op1, bits<4> crn, bits<4> crm,
853-
bits<3> op2, bit needsreg>
854-
: TLBICommon<name, op1, crn, crm, op2, needsreg>;
854+
bits<3> op2, bit needsreg, bit optionalreg>
855+
: TLBICommon<name, op1, crn, crm, op2, needsreg, optionalreg>;
855856

856857
multiclass TLBITableBase {
857858
def NAME # Table : GenericTable {
858859
let FilterClass = NAME # "Entry";
859860
let CppTypeName = NAME;
860-
let Fields = ["Name", "Encoding", "NeedsReg", "RequiresStr"];
861+
let Fields = ["Name", "Encoding", "NeedsReg", "OptionalReg", "RequiresStr"];
861862
let PrimaryKey = ["Encoding"];
862863
let PrimaryKeyName = "lookup" # NAME # "ByEncoding";
863864
}
@@ -871,60 +872,60 @@ defm TLBI : TLBITableBase;
871872
defm TLBIP : TLBITableBase;
872873

873874
multiclass TLBI<string name, bit hasTLBIP, bits<3> op1, bits<4> crn, bits<4> crm,
874-
bits<3> op2, bit needsreg = 1> {
875-
def : TLBIEntry<name, op1, crn, crm, op2, needsreg>;
876-
def : TLBIEntry<!strconcat(name, "nXS"), op1, crn, crm, op2, needsreg> {
875+
bits<3> op2, bit needsreg = 1, bit optionalreg = 0> {
876+
def : TLBIEntry<name, op1, crn, crm, op2, needsreg, optionalreg>;
877+
def : TLBIEntry<!strconcat(name, "nXS"), op1, crn, crm, op2, needsreg, optionalreg> {
877878
let Encoding{7} = 1;
878879
let ExtraRequires = ["AArch64::FeatureXS"];
879880
}
880881
if !eq(hasTLBIP, true) then {
881-
def : TLBIPEntry<name, op1, crn, crm, op2, needsreg>;
882-
def : TLBIPEntry<!strconcat(name, "nXS"), op1, crn, crm, op2, needsreg> {
882+
def : TLBIPEntry<name, op1, crn, crm, op2, needsreg, optionalreg>;
883+
def : TLBIPEntry<!strconcat(name, "nXS"), op1, crn, crm, op2, needsreg, optionalreg> {
883884
let Encoding{7} = 1;
884885
let ExtraRequires = ["AArch64::FeatureXS"];
885886
}
886887
}
887888
}
888889

889-
// hasTLBIP op1 CRn CRm op2 needsreg
890+
// hasTLBIP op1 CRn CRm op2 needsreg, optreg
890891
defm : TLBI<"IPAS2E1IS", 1, 0b100, 0b1000, 0b0000, 0b001>;
891892
defm : TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b0000, 0b101>;
892-
defm : TLBI<"VMALLE1IS", 0, 0b000, 0b1000, 0b0011, 0b000, 0>;
893-
defm : TLBI<"ALLE2IS", 0, 0b100, 0b1000, 0b0011, 0b000, 0>;
894-
defm : TLBI<"ALLE3IS", 0, 0b110, 0b1000, 0b0011, 0b000, 0>;
893+
defm : TLBI<"VMALLE1IS", 0, 0b000, 0b1000, 0b0011, 0b000, 0, 1>;
894+
defm : TLBI<"ALLE2IS", 0, 0b100, 0b1000, 0b0011, 0b000, 0, 1>;
895+
defm : TLBI<"ALLE3IS", 0, 0b110, 0b1000, 0b0011, 0b000, 0, 1>;
895896
defm : TLBI<"VAE1IS", 1, 0b000, 0b1000, 0b0011, 0b001>;
896897
defm : TLBI<"VAE2IS", 1, 0b100, 0b1000, 0b0011, 0b001>;
897898
defm : TLBI<"VAE3IS", 1, 0b110, 0b1000, 0b0011, 0b001>;
898899
defm : TLBI<"ASIDE1IS", 0, 0b000, 0b1000, 0b0011, 0b010>;
899900
defm : TLBI<"VAAE1IS", 1, 0b000, 0b1000, 0b0011, 0b011>;
900-
defm : TLBI<"ALLE1IS", 0, 0b100, 0b1000, 0b0011, 0b100, 0>;
901+
defm : TLBI<"ALLE1IS", 0, 0b100, 0b1000, 0b0011, 0b100, 0, 1>;
901902
defm : TLBI<"VALE1IS", 1, 0b000, 0b1000, 0b0011, 0b101>;
902903
defm : TLBI<"VALE2IS", 1, 0b100, 0b1000, 0b0011, 0b101>;
903904
defm : TLBI<"VALE3IS", 1, 0b110, 0b1000, 0b0011, 0b101>;
904-
defm : TLBI<"VMALLS12E1IS", 0, 0b100, 0b1000, 0b0011, 0b110, 0>;
905+
defm : TLBI<"VMALLS12E1IS", 0, 0b100, 0b1000, 0b0011, 0b110, 0, 1>;
905906
defm : TLBI<"VAALE1IS", 1, 0b000, 0b1000, 0b0011, 0b111>;
906907
defm : TLBI<"IPAS2E1", 1, 0b100, 0b1000, 0b0100, 0b001>;
907908
defm : TLBI<"IPAS2LE1", 1, 0b100, 0b1000, 0b0100, 0b101>;
908-
defm : TLBI<"VMALLE1", 0, 0b000, 0b1000, 0b0111, 0b000, 0>;
909-
defm : TLBI<"ALLE2", 0, 0b100, 0b1000, 0b0111, 0b000, 0>;
910-
defm : TLBI<"ALLE3", 0, 0b110, 0b1000, 0b0111, 0b000, 0>;
909+
defm : TLBI<"VMALLE1", 0, 0b000, 0b1000, 0b0111, 0b000, 0, 0>;
910+
defm : TLBI<"ALLE2", 0, 0b100, 0b1000, 0b0111, 0b000, 0, 0>;
911+
defm : TLBI<"ALLE3", 0, 0b110, 0b1000, 0b0111, 0b000, 0, 0>;
911912
defm : TLBI<"VAE1", 1, 0b000, 0b1000, 0b0111, 0b001>;
912913
defm : TLBI<"VAE2", 1, 0b100, 0b1000, 0b0111, 0b001>;
913914
defm : TLBI<"VAE3", 1, 0b110, 0b1000, 0b0111, 0b001>;
914915
defm : TLBI<"ASIDE1", 0, 0b000, 0b1000, 0b0111, 0b010>;
915916
defm : TLBI<"VAAE1", 1, 0b000, 0b1000, 0b0111, 0b011>;
916-
defm : TLBI<"ALLE1", 0, 0b100, 0b1000, 0b0111, 0b100, 0>;
917+
defm : TLBI<"ALLE1", 0, 0b100, 0b1000, 0b0111, 0b100, 0, 0>;
917918
defm : TLBI<"VALE1", 1, 0b000, 0b1000, 0b0111, 0b101>;
918919
defm : TLBI<"VALE2", 1, 0b100, 0b1000, 0b0111, 0b101>;
919920
defm : TLBI<"VALE3", 1, 0b110, 0b1000, 0b0111, 0b101>;
920-
defm : TLBI<"VMALLS12E1", 0, 0b100, 0b1000, 0b0111, 0b110, 0>;
921+
defm : TLBI<"VMALLS12E1", 0, 0b100, 0b1000, 0b0111, 0b110, 0, 0>;
921922
defm : TLBI<"VAALE1", 1, 0b000, 0b1000, 0b0111, 0b111>;
922923

923924
// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI)
924925
let Requires = ["AArch64::FeatureTLB_RMI"] in {
925926
// Armv8.4-A Outer Sharable TLB Maintenance instructions:
926-
// hasTLBIP op1 CRn CRm op2 needsreg
927-
defm : TLBI<"VMALLE1OS", 0, 0b000, 0b1000, 0b0001, 0b000, 0>;
927+
// hasTLBIP op1 CRn CRm op2 needsreg, optreg
928+
defm : TLBI<"VMALLE1OS", 0, 0b000, 0b1000, 0b0001, 0b000, 0, 1>;
928929
defm : TLBI<"VAE1OS", 1, 0b000, 0b1000, 0b0001, 0b001>;
929930
defm : TLBI<"ASIDE1OS", 0, 0b000, 0b1000, 0b0001, 0b010>;
930931
defm : TLBI<"VAAE1OS", 1, 0b000, 0b1000, 0b0001, 0b011>;
@@ -934,15 +935,15 @@ defm : TLBI<"IPAS2E1OS", 1, 0b100, 0b1000, 0b0100, 0b000>;
934935
defm : TLBI<"IPAS2LE1OS", 1, 0b100, 0b1000, 0b0100, 0b100>;
935936
defm : TLBI<"VAE2OS", 1, 0b100, 0b1000, 0b0001, 0b001>;
936937
defm : TLBI<"VALE2OS", 1, 0b100, 0b1000, 0b0001, 0b101>;
937-
defm : TLBI<"VMALLS12E1OS", 0, 0b100, 0b1000, 0b0001, 0b110, 0>;
938+
defm : TLBI<"VMALLS12E1OS", 0, 0b100, 0b1000, 0b0001, 0b110, 0, 1>;
938939
defm : TLBI<"VAE3OS", 1, 0b110, 0b1000, 0b0001, 0b001>;
939940
defm : TLBI<"VALE3OS", 1, 0b110, 0b1000, 0b0001, 0b101>;
940-
defm : TLBI<"ALLE2OS", 0, 0b100, 0b1000, 0b0001, 0b000, 0>;
941-
defm : TLBI<"ALLE1OS", 0, 0b100, 0b1000, 0b0001, 0b100, 0>;
942-
defm : TLBI<"ALLE3OS", 0, 0b110, 0b1000, 0b0001, 0b000, 0>;
941+
defm : TLBI<"ALLE2OS", 0, 0b100, 0b1000, 0b0001, 0b000, 0, 1>;
942+
defm : TLBI<"ALLE1OS", 0, 0b100, 0b1000, 0b0001, 0b100, 0, 1>;
943+
defm : TLBI<"ALLE3OS", 0, 0b110, 0b1000, 0b0001, 0b000, 0, 1>;
943944

944945
// Armv8.4-A TLB Range Maintenance instructions:
945-
// hasTLBIP op1 CRn CRm op2 needsreg
946+
// hasTLBIP op1 CRn CRm op2
946947
defm : TLBI<"RVAE1", 1, 0b000, 0b1000, 0b0110, 0b001>;
947948
defm : TLBI<"RVAAE1", 1, 0b000, 0b1000, 0b0110, 0b011>;
948949
defm : TLBI<"RVALE1", 1, 0b000, 0b1000, 0b0110, 0b101>;
@@ -977,18 +978,19 @@ defm : TLBI<"RVALE3OS", 1, 0b110, 0b1000, 0b0101, 0b101>;
977978

978979
// Armv9-A Realm Management Extension TLBI Instructions
979980
let Requires = ["AArch64::FeatureRME"] in {
981+
// hasTLBIP op1 CRn CRm op2 needsreg
980982
defm : TLBI<"RPAOS", 0, 0b110, 0b1000, 0b0100, 0b011>;
981983
defm : TLBI<"RPALOS", 0, 0b110, 0b1000, 0b0100, 0b111>;
982-
defm : TLBI<"PAALLOS", 0, 0b110, 0b1000, 0b0001, 0b100, 0>;
983-
defm : TLBI<"PAALL", 0, 0b110, 0b1000, 0b0111, 0b100, 0>;
984+
defm : TLBI<"PAALLOS", 0, 0b110, 0b1000, 0b0001, 0b100, 0, 0>;
985+
defm : TLBI<"PAALL", 0, 0b110, 0b1000, 0b0111, 0b100, 0, 0>;
984986
}
985987

986988
// Armv9.5-A TLBI VMALL for Dirty State
987989
let Requires = ["AArch64::FeatureTLBIW"] in {
988-
// op1, CRn, CRm, op2, needsreg
989-
defm : TLBI<"VMALLWS2E1", 0, 0b100, 0b1000, 0b0110, 0b010, 0>;
990-
defm : TLBI<"VMALLWS2E1IS", 0, 0b100, 0b1000, 0b0010, 0b010, 0>;
991-
defm : TLBI<"VMALLWS2E1OS", 0, 0b100, 0b1000, 0b0101, 0b010, 0>;
990+
// hasTLBIP op1 CRn CRm op2 needsreg, optreg
991+
defm : TLBI<"VMALLWS2E1", 0, 0b100, 0b1000, 0b0110, 0b010, 0, 0>;
992+
defm : TLBI<"VMALLWS2E1IS", 0, 0b100, 0b1000, 0b0010, 0b010, 0, 1>;
993+
defm : TLBI<"VMALLWS2E1OS", 0, 0b100, 0b1000, 0b0101, 0b010, 0, 1>;
992994
}
993995

994996
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp‎

Lines changed: 14 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -3885,6 +3885,7 @@ static const struct Extension {
38853885
{"sme-tmop", {AArch64::FeatureSME_TMOP}},
38863886
{"cmh", {AArch64::FeatureCMH}},
38873887
{"lscp", {AArch64::FeatureLSCP}},
3888+
{"tlbid", {AArch64::FeatureTLBID}},
38883889
};
38893890

38903891
static void setRequiredFeatureString(FeatureBitset FBS, std::string &Str) {
@@ -3971,6 +3972,8 @@ bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
39713972
StringRef Op = Tok.getString();
39723973
SMLoc S = Tok.getLoc();
39733974
bool ExpectRegister = true;
3975+
bool OptionalRegister = false;
3976+
bool hasAll = getSTI().hasFeature(AArch64::FeatureAll);
39743977

39753978
if (Mnemonic == "ic") {
39763979
const AArch64IC::IC *IC = AArch64IC::lookupICByName(Op);
@@ -4013,13 +4016,16 @@ bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
40134016
return TokError(Str);
40144017
}
40154018
ExpectRegister = TLBI->NeedsReg;
4019+
bool hasTLBID = getSTI().hasFeature(AArch64::FeatureTLBID);
4020+
if (hasAll || hasTLBID) {
4021+
OptionalRegister = TLBI->OptionalReg;
4022+
}
40164023
createSysAlias(TLBI->Encoding, Operands, S);
40174024
} else if (Mnemonic == "cfp" || Mnemonic == "dvp" || Mnemonic == "cpp" || Mnemonic == "cosp") {
40184025

40194026
if (Op.lower() != "rctx")
40204027
return TokError("invalid operand for prediction restriction instruction");
40214028

4022-
bool hasAll = getSTI().hasFeature(AArch64::FeatureAll);
40234029
bool hasPredres = hasAll || getSTI().hasFeature(AArch64::FeaturePredRes);
40244030
bool hasSpecres2 = hasAll || getSTI().hasFeature(AArch64::FeatureSPECRES2);
40254031

@@ -4052,10 +4058,12 @@ bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
40524058
HasRegister = true;
40534059
}
40544060

4055-
if (ExpectRegister && !HasRegister)
4056-
return TokError("specified " + Mnemonic + " op requires a register");
4057-
else if (!ExpectRegister && HasRegister)
4058-
return TokError("specified " + Mnemonic + " op does not use a register");
4061+
if (!OptionalRegister) {
4062+
if (ExpectRegister && !HasRegister)
4063+
return TokError("specified " + Mnemonic + " op requires a register");
4064+
else if (!ExpectRegister && HasRegister)
4065+
return TokError("specified " + Mnemonic + " op does not use a register");
4066+
}
40594067

40604068
if (parseToken(AsmToken::EndOfStatement, "unexpected token in argument list"))
40614069
return true;
@@ -4088,7 +4096,7 @@ bool AArch64AsmParser::parseSyspAlias(StringRef Name, SMLoc NameLoc,
40884096
return TokError("invalid operand for TLBIP instruction");
40894097
const AArch64TLBIP::TLBIP TLBIP(
40904098
TLBIPorig->Name, TLBIPorig->Encoding | (HasnXSQualifier ? (1 << 7) : 0),
4091-
TLBIPorig->NeedsReg,
4099+
TLBIPorig->NeedsReg, TLBIPorig->OptionalReg,
40924100
HasnXSQualifier
40934101
? TLBIPorig->FeaturesRequired | FeatureBitset({AArch64::FeatureXS})
40944102
: TLBIPorig->FeaturesRequired);

‎llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp‎

Lines changed: 10 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -909,7 +909,8 @@ bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
909909
Encoding |= CnVal << 7;
910910
Encoding |= Op1Val << 11;
911911

912-
bool NeedsReg;
912+
bool NeedsReg = false;
913+
bool OptionalReg = false;
913914
std::string Ins;
914915
std::string Name;
915916

@@ -1004,6 +1005,9 @@ bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
10041005
return false;
10051006

10061007
NeedsReg = TLBI->NeedsReg;
1008+
if (STI.hasFeature(AArch64::FeatureAll) ||
1009+
STI.hasFeature(AArch64::FeatureTLBID))
1010+
OptionalReg = TLBI->OptionalReg;
10071011
Ins = "tlbi\t";
10081012
Name = std::string(TLBI->Name);
10091013
}
@@ -1013,18 +1017,20 @@ bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
10131017
StringRef Reg = getRegisterName(MI->getOperand(4).getReg());
10141018
bool NotXZR = Reg != "xzr";
10151019

1016-
// If a mandatory is not specified in the TableGen
1020+
// If a mandatory or optional register is not specified in the TableGen
10171021
// (i.e. no register operand should be present), and the register value
10181022
// is not xzr/x31, then disassemble to a SYS alias instead.
1019-
if (NotXZR && !NeedsReg)
1023+
if (NotXZR && !NeedsReg && !OptionalReg)
10201024
return false;
10211025

10221026
std::string Str = Ins + Name;
10231027
llvm::transform(Str, Str.begin(), ::tolower);
10241028

10251029
O << '\t' << Str;
10261030

1027-
if (NeedsReg)
1031+
// For optional registers, don't print the value if it's xzr/x31
1032+
// since this defaults to xzr/x31 if register is not specified.
1033+
if (NeedsReg || (OptionalReg && NotXZR))
10281034
O << ", " << Reg;
10291035

10301036
return true;

‎llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h‎

Lines changed: 17 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -409,6 +409,16 @@ struct SysAliasReg : SysAlias {
409409
: SysAlias(N, E, F), NeedsReg(R) {}
410410
};
411411

412+
struct SysAliasOptionalReg : SysAlias {
413+
bool NeedsReg;
414+
bool OptionalReg;
415+
constexpr SysAliasOptionalReg(const char *N, uint16_t E, bool R, bool O)
416+
: SysAlias(N, E), NeedsReg(R), OptionalReg(O) {}
417+
constexpr SysAliasOptionalReg(const char *N, uint16_t E, bool R, bool O,
418+
FeatureBitset F)
419+
: SysAlias(N, E, F), NeedsReg(R), OptionalReg(O) {}
420+
};
421+
412422
struct SysAliasImm : SysAlias {
413423
uint16_t ImmValue;
414424
constexpr SysAliasImm(const char *N, uint16_t E, uint16_t I)
@@ -796,16 +806,16 @@ namespace AArch64SysReg {
796806
}
797807

798808
namespace AArch64TLBI {
799-
struct TLBI : SysAliasReg {
800-
using SysAliasReg::SysAliasReg;
801-
};
802-
#define GET_TLBITable_DECL
803-
#include "AArch64GenSystemOperands.inc"
809+
struct TLBI : SysAliasOptionalReg {
810+
using SysAliasOptionalReg::SysAliasOptionalReg;
811+
};
812+
#define GET_TLBITable_DECL
813+
#include "AArch64GenSystemOperands.inc"
804814
}
805815

806816
namespace AArch64TLBIP {
807-
struct TLBIP : SysAliasReg {
808-
using SysAliasReg::SysAliasReg;
817+
struct TLBIP : SysAliasOptionalReg {
818+
using SysAliasOptionalReg::SysAliasOptionalReg;
809819
};
810820
#define GET_TLBIPTable_DECL
811821
#include "AArch64GenSystemOperands.inc"

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