review comments

Author: shiltian

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

@@ -17671,10 +17671,7 @@ SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI_,
     case 'v':
       switch (BitWidth) {
       case 1:
-        RC = Subtarget->has1024AddressableVGPRs()
-                 ? &AMDGPU::VGPR_32_Lo256RegClass
-                 : &AMDGPU::VGPR_32RegClass;
-        break;
+        return std::pair(0U, nullptr);
       case 16:
         RC = Subtarget->useRealTrue16Insts() ? &AMDGPU::VGPR_16RegClass
                                              : &AMDGPU::VGPR_32_Lo256RegClass;

llvm/test/CodeGen/AMDGPU/inline-asm.ll

@@ -363,15 +363,3 @@ define void @mixed_def_sgpr_vgpr_def_asm() {
   call void asm sideeffect "; use $0 ", "{s[4:5]}"(i64 %sgpr.add)
   ret void
 }
-
-define void @i1_used_as_vgpr_operand(ptr %p, i1 %b) {
-; CHECK-LABEL: i1_used_as_vgpr_operand:
-; CHECK:       ; %bb.0:
-; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    ;;#ASMSTART
-; CHECK-NEXT:    global_store_byte v[0:1], v2, off glc slc
-; CHECK-NEXT:    ;;#ASMEND
-; CHECK-NEXT:    s_setpc_b64 s[30:31]
-  tail call void asm sideeffect "global_store_byte $0, $1, off glc slc", "v,v"(ptr %p, i1 %b)
-  ret void
-}

llvm/test/CodeGen/AMDGPU/inlineasm-mismatched-size-error.ll

@@ -153,3 +153,9 @@ define <4 x i32> @misaligned_sgpr_4xi32_out_2() {
   %asm = call <4 x i32> asm sideeffect "; def $0", "={s[2:5]}"()
   ret <4 x i32> %asm
 }
+
+; ERR: error: couldn't allocate input reg for constraint 'v'
+define void @i1_used_as_vgpr_operand(ptr %p, i1 %b) {
+  tail call void asm sideeffect "global_store_byte $0, $1, off glc slc", "v,v"(ptr %p, i1 %b)
+  ret void
+}