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[AMDGPU] Extending wave reduction intrinsics for i64 types - 1
Supporting Min/Max Operations: `min`, `max`, `umin`, `umax`
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5 files changed

+390
-1
lines changed

5 files changed

+390
-1
lines changed

‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp‎

Lines changed: 11 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5324,12 +5324,16 @@ static MachineBasicBlock *Expand64BitScalarArithmetic(MachineInstr &MI,
53245324
static uint32_t getIdentityValueFor32BitWaveReduction(unsigned Opc) {
53255325
switch (Opc) {
53265326
case AMDGPU::S_MIN_U32:
5327+
case AMDGPU::V_CMP_LT_U64_e64: // umin.u64
53275328
return std::numeric_limits<uint32_t>::max();
53285329
case AMDGPU::S_MIN_I32:
5330+
case AMDGPU::V_CMP_LT_I64_e64: // min.i64
53295331
return std::numeric_limits<int32_t>::max();
53305332
case AMDGPU::S_MAX_U32:
5333+
case AMDGPU::V_CMP_GT_U64_e64: // umax.u64
53315334
return std::numeric_limits<uint32_t>::min();
53325335
case AMDGPU::S_MAX_I32:
5336+
case AMDGPU::V_CMP_GT_I64_e64: // max.i64
53335337
return std::numeric_limits<int32_t>::min();
53345338
case AMDGPU::S_ADD_I32:
53355339
case AMDGPU::S_SUB_I32:
@@ -5385,16 +5389,22 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
53855389
bool isSGPR = TRI->isSGPRClass(MRI.getRegClass(SrcReg));
53865390
Register DstReg = MI.getOperand(0).getReg();
53875391
MachineBasicBlock *RetBB = nullptr;
5392+
bool is32BitOpc = TRI->getRegSizeInBits(*MRI.getRegClass(DstReg)) == 32;
53885393
if (isSGPR) {
53895394
switch (Opc) {
53905395
case AMDGPU::S_MIN_U32:
5396+
case AMDGPU::V_CMP_LT_U64_e64: /*umin*/
53915397
case AMDGPU::S_MIN_I32:
5398+
case AMDGPU::V_CMP_LT_I64_e64: /*min*/
53925399
case AMDGPU::S_MAX_U32:
5400+
case AMDGPU::V_CMP_GT_U64_e64: /*umax*/
53935401
case AMDGPU::S_MAX_I32:
5402+
case AMDGPU::V_CMP_GT_I64_e64: /*max*/
53945403
case AMDGPU::S_AND_B32:
53955404
case AMDGPU::S_OR_B32: {
53965405
// Idempotent operations.
5397-
BuildMI(BB, MI, DL, TII->get(AMDGPU::S_MOV_B32), DstReg).addReg(SrcReg);
5406+
unsigned movOpc = is32BitOpc ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
5407+
BuildMI(BB, MI, DL, TII->get(movOpc), DstReg).addReg(SrcReg);
53985408
RetBB = &BB;
53995409
break;
54005410
}

‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll‎

Lines changed: 92 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1269,9 +1269,15 @@ define void @divergent_value_i64(ptr addrspace(1) %out, i64 %id.x) {
12691269
; GFX8DAGISEL-LABEL: divergent_value_i64:
12701270
; GFX8DAGISEL: ; %bb.0: ; %entry
12711271
; GFX8DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1272+
<<<<<<< HEAD
12721273
; GFX8DAGISEL-NEXT: s_mov_b32 s4, 0
12731274
; GFX8DAGISEL-NEXT: s_brev_b32 s5, 1
12741275
; GFX8DAGISEL-NEXT: s_mov_b64 s[6:7], exec
1276+
=======
1277+
; GFX8DAGISEL-NEXT: s_mov_b64 s[6:7], exec
1278+
; GFX8DAGISEL-NEXT: s_brev_b32 s5, 1
1279+
; GFX8DAGISEL-NEXT: s_mov_b32 s4, 0
1280+
>>>>>>> 381cb9fada25 ([AMDGPU] Extending wave reduction intrinsics for `i64` types - 1)
12751281
; GFX8DAGISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
12761282
; GFX8DAGISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
12771283
; GFX8DAGISEL-NEXT: v_mov_b32_e32 v4, s4
@@ -1294,9 +1300,15 @@ define void @divergent_value_i64(ptr addrspace(1) %out, i64 %id.x) {
12941300
; GFX8GISEL-LABEL: divergent_value_i64:
12951301
; GFX8GISEL: ; %bb.0: ; %entry
12961302
; GFX8GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1303+
<<<<<<< HEAD
12971304
; GFX8GISEL-NEXT: s_mov_b32 s4, 0
12981305
; GFX8GISEL-NEXT: s_brev_b32 s5, 1
12991306
; GFX8GISEL-NEXT: s_mov_b64 s[6:7], exec
1307+
=======
1308+
; GFX8GISEL-NEXT: s_mov_b64 s[6:7], exec
1309+
; GFX8GISEL-NEXT: s_brev_b32 s5, 1
1310+
; GFX8GISEL-NEXT: s_mov_b32 s4, 0
1311+
>>>>>>> 381cb9fada25 ([AMDGPU] Extending wave reduction intrinsics for `i64` types - 1)
13001312
; GFX8GISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
13011313
; GFX8GISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
13021314
; GFX8GISEL-NEXT: v_mov_b32_e32 v4, s4
@@ -1319,9 +1331,15 @@ define void @divergent_value_i64(ptr addrspace(1) %out, i64 %id.x) {
13191331
; GFX9DAGISEL-LABEL: divergent_value_i64:
13201332
; GFX9DAGISEL: ; %bb.0: ; %entry
13211333
; GFX9DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1334+
<<<<<<< HEAD
13221335
; GFX9DAGISEL-NEXT: s_mov_b32 s4, 0
13231336
; GFX9DAGISEL-NEXT: s_brev_b32 s5, 1
13241337
; GFX9DAGISEL-NEXT: s_mov_b64 s[6:7], exec
1338+
=======
1339+
; GFX9DAGISEL-NEXT: s_mov_b64 s[6:7], exec
1340+
; GFX9DAGISEL-NEXT: s_brev_b32 s5, 1
1341+
; GFX9DAGISEL-NEXT: s_mov_b32 s4, 0
1342+
>>>>>>> 381cb9fada25 ([AMDGPU] Extending wave reduction intrinsics for `i64` types - 1)
13251343
; GFX9DAGISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
13261344
; GFX9DAGISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
13271345
; GFX9DAGISEL-NEXT: v_mov_b32_e32 v4, s4
@@ -1344,9 +1362,15 @@ define void @divergent_value_i64(ptr addrspace(1) %out, i64 %id.x) {
13441362
; GFX9GISEL-LABEL: divergent_value_i64:
13451363
; GFX9GISEL: ; %bb.0: ; %entry
13461364
; GFX9GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1365+
<<<<<<< HEAD
13471366
; GFX9GISEL-NEXT: s_mov_b32 s4, 0
13481367
; GFX9GISEL-NEXT: s_brev_b32 s5, 1
13491368
; GFX9GISEL-NEXT: s_mov_b64 s[6:7], exec
1369+
=======
1370+
; GFX9GISEL-NEXT: s_mov_b64 s[6:7], exec
1371+
; GFX9GISEL-NEXT: s_brev_b32 s5, 1
1372+
; GFX9GISEL-NEXT: s_mov_b32 s4, 0
1373+
>>>>>>> 381cb9fada25 ([AMDGPU] Extending wave reduction intrinsics for `i64` types - 1)
13501374
; GFX9GISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
13511375
; GFX9GISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
13521376
; GFX9GISEL-NEXT: v_mov_b32_e32 v4, s4
@@ -1369,9 +1393,15 @@ define void @divergent_value_i64(ptr addrspace(1) %out, i64 %id.x) {
13691393
; GFX1064DAGISEL-LABEL: divergent_value_i64:
13701394
; GFX1064DAGISEL: ; %bb.0: ; %entry
13711395
; GFX1064DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1396+
<<<<<<< HEAD
13721397
; GFX1064DAGISEL-NEXT: s_mov_b32 s4, 0
13731398
; GFX1064DAGISEL-NEXT: s_brev_b32 s5, 1
13741399
; GFX1064DAGISEL-NEXT: s_mov_b64 s[6:7], exec
1400+
=======
1401+
; GFX1064DAGISEL-NEXT: s_mov_b64 s[6:7], exec
1402+
; GFX1064DAGISEL-NEXT: s_brev_b32 s5, 1
1403+
; GFX1064DAGISEL-NEXT: s_mov_b32 s4, 0
1404+
>>>>>>> 381cb9fada25 ([AMDGPU] Extending wave reduction intrinsics for `i64` types - 1)
13751405
; GFX1064DAGISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
13761406
; GFX1064DAGISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
13771407
; GFX1064DAGISEL-NEXT: v_mov_b32_e32 v4, s4
@@ -1393,9 +1423,15 @@ define void @divergent_value_i64(ptr addrspace(1) %out, i64 %id.x) {
13931423
; GFX1064GISEL-LABEL: divergent_value_i64:
13941424
; GFX1064GISEL: ; %bb.0: ; %entry
13951425
; GFX1064GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1426+
<<<<<<< HEAD
13961427
; GFX1064GISEL-NEXT: s_mov_b32 s4, 0
13971428
; GFX1064GISEL-NEXT: s_brev_b32 s5, 1
13981429
; GFX1064GISEL-NEXT: s_mov_b64 s[6:7], exec
1430+
=======
1431+
; GFX1064GISEL-NEXT: s_mov_b64 s[6:7], exec
1432+
; GFX1064GISEL-NEXT: s_brev_b32 s5, 1
1433+
; GFX1064GISEL-NEXT: s_mov_b32 s4, 0
1434+
>>>>>>> 381cb9fada25 ([AMDGPU] Extending wave reduction intrinsics for `i64` types - 1)
13991435
; GFX1064GISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
14001436
; GFX1064GISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
14011437
; GFX1064GISEL-NEXT: v_mov_b32_e32 v4, s4
@@ -1417,9 +1453,15 @@ define void @divergent_value_i64(ptr addrspace(1) %out, i64 %id.x) {
14171453
; GFX1032DAGISEL-LABEL: divergent_value_i64:
14181454
; GFX1032DAGISEL: ; %bb.0: ; %entry
14191455
; GFX1032DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1456+
<<<<<<< HEAD
14201457
; GFX1032DAGISEL-NEXT: s_mov_b32 s4, 0
14211458
; GFX1032DAGISEL-NEXT: s_brev_b32 s5, 1
14221459
; GFX1032DAGISEL-NEXT: s_mov_b32 s6, exec_lo
1460+
=======
1461+
; GFX1032DAGISEL-NEXT: s_mov_b32 s6, exec_lo
1462+
; GFX1032DAGISEL-NEXT: s_brev_b32 s5, 1
1463+
; GFX1032DAGISEL-NEXT: s_mov_b32 s4, 0
1464+
>>>>>>> 381cb9fada25 ([AMDGPU] Extending wave reduction intrinsics for `i64` types - 1)
14231465
; GFX1032DAGISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
14241466
; GFX1032DAGISEL-NEXT: s_ff1_i32_b32 s7, s6
14251467
; GFX1032DAGISEL-NEXT: v_mov_b32_e32 v4, s4
@@ -1441,9 +1483,15 @@ define void @divergent_value_i64(ptr addrspace(1) %out, i64 %id.x) {
14411483
; GFX1032GISEL-LABEL: divergent_value_i64:
14421484
; GFX1032GISEL: ; %bb.0: ; %entry
14431485
; GFX1032GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1486+
<<<<<<< HEAD
14441487
; GFX1032GISEL-NEXT: s_mov_b32 s4, 0
14451488
; GFX1032GISEL-NEXT: s_brev_b32 s5, 1
14461489
; GFX1032GISEL-NEXT: s_mov_b32 s6, exec_lo
1490+
=======
1491+
; GFX1032GISEL-NEXT: s_mov_b32 s6, exec_lo
1492+
; GFX1032GISEL-NEXT: s_brev_b32 s5, 1
1493+
; GFX1032GISEL-NEXT: s_mov_b32 s4, 0
1494+
>>>>>>> 381cb9fada25 ([AMDGPU] Extending wave reduction intrinsics for `i64` types - 1)
14471495
; GFX1032GISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
14481496
; GFX1032GISEL-NEXT: s_ff1_i32_b32 s7, s6
14491497
; GFX1032GISEL-NEXT: v_mov_b32_e32 v4, s4
@@ -1465,16 +1513,27 @@ define void @divergent_value_i64(ptr addrspace(1) %out, i64 %id.x) {
14651513
; GFX1164DAGISEL-LABEL: divergent_value_i64:
14661514
; GFX1164DAGISEL: ; %bb.0: ; %entry
14671515
; GFX1164DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1516+
<<<<<<< HEAD
14681517
; GFX1164DAGISEL-NEXT: s_mov_b32 s0, 0
14691518
; GFX1164DAGISEL-NEXT: s_brev_b32 s1, 1
14701519
; GFX1164DAGISEL-NEXT: s_mov_b64 s[2:3], exec
14711520
; GFX1164DAGISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
14721521
; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
1522+
=======
1523+
; GFX1164DAGISEL-NEXT: s_mov_b64 s[2:3], exec
1524+
; GFX1164DAGISEL-NEXT: s_brev_b32 s1, 1
1525+
; GFX1164DAGISEL-NEXT: s_mov_b32 s0, 0
1526+
; GFX1164DAGISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
1527+
>>>>>>> 381cb9fada25 ([AMDGPU] Extending wave reduction intrinsics for `i64` types - 1)
14731528
; GFX1164DAGISEL-NEXT: s_ctz_i32_b64 s8, s[2:3]
14741529
; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v4, s0
14751530
; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v5, s1
14761531
; GFX1164DAGISEL-NEXT: v_readlane_b32 s4, v2, s8
14771532
; GFX1164DAGISEL-NEXT: v_readlane_b32 s5, v3, s8
1533+
<<<<<<< HEAD
1534+
=======
1535+
; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
1536+
>>>>>>> 381cb9fada25 ([AMDGPU] Extending wave reduction intrinsics for `i64` types - 1)
14781537
; GFX1164DAGISEL-NEXT: v_cmp_gt_i64_e32 vcc, s[4:5], v[4:5]
14791538
; GFX1164DAGISEL-NEXT: s_and_b64 s[6:7], vcc, s[2:3]
14801539
; GFX1164DAGISEL-NEXT: s_bitset0_b64 s[2:3], s8
@@ -1490,16 +1549,27 @@ define void @divergent_value_i64(ptr addrspace(1) %out, i64 %id.x) {
14901549
; GFX1164GISEL-LABEL: divergent_value_i64:
14911550
; GFX1164GISEL: ; %bb.0: ; %entry
14921551
; GFX1164GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1552+
<<<<<<< HEAD
14931553
; GFX1164GISEL-NEXT: s_mov_b32 s0, 0
14941554
; GFX1164GISEL-NEXT: s_brev_b32 s1, 1
14951555
; GFX1164GISEL-NEXT: s_mov_b64 s[2:3], exec
14961556
; GFX1164GISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
14971557
; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
1558+
=======
1559+
; GFX1164GISEL-NEXT: s_mov_b64 s[2:3], exec
1560+
; GFX1164GISEL-NEXT: s_brev_b32 s1, 1
1561+
; GFX1164GISEL-NEXT: s_mov_b32 s0, 0
1562+
; GFX1164GISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
1563+
>>>>>>> 381cb9fada25 ([AMDGPU] Extending wave reduction intrinsics for `i64` types - 1)
14981564
; GFX1164GISEL-NEXT: s_ctz_i32_b64 s8, s[2:3]
14991565
; GFX1164GISEL-NEXT: v_mov_b32_e32 v4, s0
15001566
; GFX1164GISEL-NEXT: v_mov_b32_e32 v5, s1
15011567
; GFX1164GISEL-NEXT: v_readlane_b32 s4, v2, s8
15021568
; GFX1164GISEL-NEXT: v_readlane_b32 s5, v3, s8
1569+
<<<<<<< HEAD
1570+
=======
1571+
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
1572+
>>>>>>> 381cb9fada25 ([AMDGPU] Extending wave reduction intrinsics for `i64` types - 1)
15031573
; GFX1164GISEL-NEXT: v_cmp_gt_i64_e32 vcc, s[4:5], v[4:5]
15041574
; GFX1164GISEL-NEXT: s_and_b64 s[6:7], vcc, s[2:3]
15051575
; GFX1164GISEL-NEXT: s_bitset0_b64 s[2:3], s8
@@ -1515,15 +1585,26 @@ define void @divergent_value_i64(ptr addrspace(1) %out, i64 %id.x) {
15151585
; GFX1132DAGISEL-LABEL: divergent_value_i64:
15161586
; GFX1132DAGISEL: ; %bb.0: ; %entry
15171587
; GFX1132DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1588+
<<<<<<< HEAD
15181589
; GFX1132DAGISEL-NEXT: s_mov_b32 s0, 0
15191590
; GFX1132DAGISEL-NEXT: s_brev_b32 s1, 1
15201591
; GFX1132DAGISEL-NEXT: s_mov_b32 s2, exec_lo
15211592
; GFX1132DAGISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
15221593
; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
1594+
=======
1595+
; GFX1132DAGISEL-NEXT: s_mov_b32 s2, exec_lo
1596+
; GFX1132DAGISEL-NEXT: s_brev_b32 s1, 1
1597+
; GFX1132DAGISEL-NEXT: s_mov_b32 s0, 0
1598+
; GFX1132DAGISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
1599+
>>>>>>> 381cb9fada25 ([AMDGPU] Extending wave reduction intrinsics for `i64` types - 1)
15231600
; GFX1132DAGISEL-NEXT: s_ctz_i32_b32 s3, s2
15241601
; GFX1132DAGISEL-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v5, s1
15251602
; GFX1132DAGISEL-NEXT: v_readlane_b32 s4, v2, s3
15261603
; GFX1132DAGISEL-NEXT: v_readlane_b32 s5, v3, s3
1604+
<<<<<<< HEAD
1605+
=======
1606+
; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
1607+
>>>>>>> 381cb9fada25 ([AMDGPU] Extending wave reduction intrinsics for `i64` types - 1)
15271608
; GFX1132DAGISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[4:5], v[4:5]
15281609
; GFX1132DAGISEL-NEXT: s_and_b32 s6, vcc_lo, s2
15291610
; GFX1132DAGISEL-NEXT: s_bitset0_b32 s2, s3
@@ -1538,15 +1619,26 @@ define void @divergent_value_i64(ptr addrspace(1) %out, i64 %id.x) {
15381619
; GFX1132GISEL-LABEL: divergent_value_i64:
15391620
; GFX1132GISEL: ; %bb.0: ; %entry
15401621
; GFX1132GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1622+
<<<<<<< HEAD
15411623
; GFX1132GISEL-NEXT: s_mov_b32 s0, 0
15421624
; GFX1132GISEL-NEXT: s_brev_b32 s1, 1
15431625
; GFX1132GISEL-NEXT: s_mov_b32 s2, exec_lo
15441626
; GFX1132GISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
15451627
; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
1628+
=======
1629+
; GFX1132GISEL-NEXT: s_mov_b32 s2, exec_lo
1630+
; GFX1132GISEL-NEXT: s_brev_b32 s1, 1
1631+
; GFX1132GISEL-NEXT: s_mov_b32 s0, 0
1632+
; GFX1132GISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
1633+
>>>>>>> 381cb9fada25 ([AMDGPU] Extending wave reduction intrinsics for `i64` types - 1)
15461634
; GFX1132GISEL-NEXT: s_ctz_i32_b32 s3, s2
15471635
; GFX1132GISEL-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v5, s1
15481636
; GFX1132GISEL-NEXT: v_readlane_b32 s4, v2, s3
15491637
; GFX1132GISEL-NEXT: v_readlane_b32 s5, v3, s3
1638+
<<<<<<< HEAD
1639+
=======
1640+
; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
1641+
>>>>>>> 381cb9fada25 ([AMDGPU] Extending wave reduction intrinsics for `i64` types - 1)
15501642
; GFX1132GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[4:5], v[4:5]
15511643
; GFX1132GISEL-NEXT: s_and_b32 s6, vcc_lo, s2
15521644
; GFX1132GISEL-NEXT: s_bitset0_b32 s2, s3

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