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Ting WangTing Wang
Ting Wang
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Ting Wang
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[PowerPC] Add vector pair calling convention for AIX
This is AIX part of update after https://reviews.llvm.org/D117225 Fixed the issue that AIX64 with vector pair enabled saw redundant spill/reload of callee saved vector registers. Based on original patch by: Kai Luo Reviewed By: lkail Differential Revision: https://reviews.llvm.org/D133466
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4 files changed

+49
-77
lines changed

4 files changed

+49
-77
lines changed

‎llvm/lib/Target/PowerPC/PPCCallingConv.td‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -386,3 +386,9 @@ def CSR_SVR64_ColdCC_R2_VSRP : CalleeSavedRegs<(add CSR_SVR64_ColdCC_VSRP, X2)>;
386386

387387
def CSR_64_AllRegs_VSRP :
388388
CalleeSavedRegs<(add CSR_64_AllRegs_VSX, CSR_ALL_VSRP)>;
389+
390+
def CSR_AIX64_VSRP : CalleeSavedRegs<(add CSR_PPC64_Altivec, CSR_VSRP)>;
391+
392+
def CSR_AIX64_R2_VSRP : CalleeSavedRegs<(add CSR_AIX64_VSRP, X2)>;
393+
394+
def CSR_AIX32_VSRP : CalleeSavedRegs<(add CSR_AIX32_Altivec, CSR_VSRP)>;

‎llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp‎

Lines changed: 15 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -237,8 +237,14 @@ PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
237237
}
238238
// Standard calling convention CSRs.
239239
if (TM.isPPC64()) {
240-
if (Subtarget.pairedVectorMemops())
240+
if (Subtarget.pairedVectorMemops()) {
241+
if (Subtarget.isAIXABI()) {
242+
if (!TM.getAIXExtendedAltivecABI())
243+
return SaveR2 ? CSR_PPC64_R2_SaveList : CSR_PPC64_SaveList;
244+
return SaveR2 ? CSR_AIX64_R2_VSRP_SaveList : CSR_AIX64_VSRP_SaveList;
245+
}
241246
return SaveR2 ? CSR_SVR464_R2_VSRP_SaveList : CSR_SVR464_VSRP_SaveList;
247+
}
242248
if (Subtarget.hasAltivec() &&
243249
(!Subtarget.isAIXABI() || TM.getAIXExtendedAltivecABI())) {
244250
return SaveR2 ? CSR_PPC64_R2_Altivec_SaveList
@@ -248,6 +254,9 @@ PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
248254
}
249255
// 32-bit targets.
250256
if (Subtarget.isAIXABI()) {
257+
if (Subtarget.pairedVectorMemops())
258+
return TM.getAIXExtendedAltivecABI() ? CSR_AIX32_VSRP_SaveList
259+
: CSR_AIX32_SaveList;
251260
if (Subtarget.hasAltivec())
252261
return TM.getAIXExtendedAltivecABI() ? CSR_AIX32_Altivec_SaveList
253262
: CSR_AIX32_SaveList;
@@ -286,6 +295,11 @@ PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
286295
}
287296

288297
if (Subtarget.isAIXABI()) {
298+
if (Subtarget.pairedVectorMemops()) {
299+
if (!TM.getAIXExtendedAltivecABI())
300+
return TM.isPPC64() ? CSR_PPC64_RegMask : CSR_AIX32_RegMask;
301+
return TM.isPPC64() ? CSR_AIX64_VSRP_RegMask : CSR_AIX32_VSRP_RegMask;
302+
}
289303
return TM.isPPC64()
290304
? ((Subtarget.hasAltivec() && TM.getAIXExtendedAltivecABI())
291305
? CSR_PPC64_Altivec_RegMask

‎llvm/test/CodeGen/PowerPC/aix64-vector-pair-cc-spills.ll‎

Lines changed: 26 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -3,32 +3,20 @@
33
; RUN: llc -O0 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr10 -vec-extabi -stop-after=prologepilog -verify-machineinstrs < %s | \
44
; RUN: FileCheck --check-prefix=CHECK-VEXT %s
55

6-
; Error pattern will be fixed in https://reviews.llvm.org/D133466
76
; CHECK-LABEL: name: foo
8-
; CHECK: spill-slot
9-
; CHECK-NEXT: callee-saved-register: '$v31'
10-
; CHECK: spill-slot
11-
; CHECK-NEXT: callee-saved-register: '$v30'
12-
; CHECK: spill-slot
13-
; CHECK-NEXT: callee-saved-register: '$v29'
14-
; CHECK: spill-slot
15-
; CHECK-NEXT: callee-saved-register: '$v28'
16-
; CHECK: spill-slot
17-
; CHECK-NEXT: callee-saved-register: '$v27'
18-
; CHECK: spill-slot
19-
; CHECK-NEXT: callee-saved-register: '$v26'
20-
; CHECK: spill-slot
21-
; CHECK-NEXT: callee-saved-register: '$v25'
22-
; CHECK: spill-slot
23-
; CHECK-NEXT: callee-saved-register: '$v24'
24-
; CHECK: spill-slot
25-
; CHECK-NEXT: callee-saved-register: '$v23'
26-
; CHECK: spill-slot
27-
; CHECK-NEXT: callee-saved-register: '$v22'
28-
; CHECK: spill-slot
29-
; CHECK-NEXT: callee-saved-register: '$v21'
30-
; CHECK: spill-slot
31-
; CHECK-NEXT: callee-saved-register: '$v20'
7+
; CHECK-NOT: spill-slot
8+
; CHECK-NOT: callee-saved-register: '$v31'
9+
; CHECK-NOT: callee-saved-register: '$v30'
10+
; CHECK-NOT: callee-saved-register: '$v29'
11+
; CHECK-NOT: callee-saved-register: '$v28'
12+
; CHECK-NOT: callee-saved-register: '$v27'
13+
; CHECK-NOT: callee-saved-register: '$v26'
14+
; CHECK-NOT: callee-saved-register: '$v25'
15+
; CHECK-NOT: callee-saved-register: '$v24'
16+
; CHECK-NOT: callee-saved-register: '$v23'
17+
; CHECK-NOT: callee-saved-register: '$v22'
18+
; CHECK-NOT: callee-saved-register: '$v21'
19+
; CHECK-NOT: callee-saved-register: '$v20'
3220

3321
; CHECK-VEXT-LABEL: name: foo
3422
; CHECK-VEXT-NOT: spill-slot
@@ -50,32 +38,20 @@ entry:
5038
ret void
5139
}
5240

53-
; Error pattern will be fixed in https://reviews.llvm.org/D133466
5441
; CHECK-LABEL: name: spill
55-
; CHECK: spill-slot
56-
; CHECK-NEXT: callee-saved-register: '$v31'
57-
; CHECK: spill-slot
58-
; CHECK-NEXT: callee-saved-register: '$v30'
59-
; CHECK: spill-slot
60-
; CHECK-NEXT: callee-saved-register: '$v29'
61-
; CHECK: spill-slot
62-
; CHECK-NEXT: callee-saved-register: '$v28'
63-
; CHECK: spill-slot
64-
; CHECK-NEXT: callee-saved-register: '$v27'
65-
; CHECK: spill-slot
66-
; CHECK-NEXT: callee-saved-register: '$v26'
67-
; CHECK: spill-slot
68-
; CHECK-NEXT: callee-saved-register: '$v25'
69-
; CHECK: spill-slot
70-
; CHECK-NEXT: callee-saved-register: '$v24'
71-
; CHECK: spill-slot
72-
; CHECK-NEXT: callee-saved-register: '$v23'
73-
; CHECK: spill-slot
74-
; CHECK-NEXT: callee-saved-register: '$v22'
75-
; CHECK: spill-slot
76-
; CHECK-NEXT: callee-saved-register: '$v21'
77-
; CHECK: spill-slot
78-
; CHECK-NEXT: callee-saved-register: '$v20'
42+
; CHECK-NOT: spill-slot
43+
; CHECK-NOT: callee-saved-register: '$v31'
44+
; CHECK-NOT: callee-saved-register: '$v30'
45+
; CHECK-NOT: callee-saved-register: '$v29'
46+
; CHECK-NOT: callee-saved-register: '$v28'
47+
; CHECK-NOT: callee-saved-register: '$v27'
48+
; CHECK-NOT: callee-saved-register: '$v26'
49+
; CHECK-NOT: callee-saved-register: '$v25'
50+
; CHECK-NOT: callee-saved-register: '$v24'
51+
; CHECK-NOT: callee-saved-register: '$v23'
52+
; CHECK-NOT: callee-saved-register: '$v22'
53+
; CHECK-NOT: callee-saved-register: '$v21'
54+
; CHECK-NOT: callee-saved-register: '$v20'
7955

8056
; CHECK-VEXT-LABEL: name: spill
8157
; CHECK-VEXT: spill-slot

‎llvm/test/CodeGen/PowerPC/aix64-virtual-call-no-spills.ll‎

Lines changed: 2 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -9,19 +9,7 @@ define dso_local noundef signext i32 @virtualCall(ptr noundef %b) #0 {
99
; CHECK: # %bb.0: # %entry
1010
; CHECK-NEXT: mflr 0
1111
; CHECK-NEXT: std 0, 16(1)
12-
; CHECK-NEXT: stdu 1, -320(1)
13-
; CHECK-NEXT: stxv 52, 128(1) # 16-byte Folded Spill
14-
; CHECK-NEXT: stxv 53, 144(1) # 16-byte Folded Spill
15-
; CHECK-NEXT: stxv 54, 160(1) # 16-byte Folded Spill
16-
; CHECK-NEXT: stxv 55, 176(1) # 16-byte Folded Spill
17-
; CHECK-NEXT: stxv 56, 192(1) # 16-byte Folded Spill
18-
; CHECK-NEXT: stxv 57, 208(1) # 16-byte Folded Spill
19-
; CHECK-NEXT: stxv 58, 224(1) # 16-byte Folded Spill
20-
; CHECK-NEXT: stxv 59, 240(1) # 16-byte Folded Spill
21-
; CHECK-NEXT: stxv 60, 256(1) # 16-byte Folded Spill
22-
; CHECK-NEXT: stxv 61, 272(1) # 16-byte Folded Spill
23-
; CHECK-NEXT: stxv 62, 288(1) # 16-byte Folded Spill
24-
; CHECK-NEXT: stxv 63, 304(1) # 16-byte Folded Spill
12+
; CHECK-NEXT: stdu 1, -128(1)
2513
; CHECK-NEXT: std 3, 120(1)
2614
; CHECK-NEXT: ld 3, 120(1)
2715
; CHECK-NEXT: ld 4, 0(3)
@@ -37,19 +25,7 @@ define dso_local noundef signext i32 @virtualCall(ptr noundef %b) #0 {
3725
; CHECK-NEXT: ld 2, 40(1)
3826
; CHECK-NEXT: # kill: def $r3 killed $r3 killed $x3
3927
; CHECK-NEXT: extsw 3, 3
40-
; CHECK-NEXT: lxv 63, 304(1) # 16-byte Folded Reload
41-
; CHECK-NEXT: lxv 62, 288(1) # 16-byte Folded Reload
42-
; CHECK-NEXT: lxv 61, 272(1) # 16-byte Folded Reload
43-
; CHECK-NEXT: lxv 60, 256(1) # 16-byte Folded Reload
44-
; CHECK-NEXT: lxv 59, 240(1) # 16-byte Folded Reload
45-
; CHECK-NEXT: lxv 58, 224(1) # 16-byte Folded Reload
46-
; CHECK-NEXT: lxv 57, 208(1) # 16-byte Folded Reload
47-
; CHECK-NEXT: lxv 56, 192(1) # 16-byte Folded Reload
48-
; CHECK-NEXT: lxv 55, 176(1) # 16-byte Folded Reload
49-
; CHECK-NEXT: lxv 54, 160(1) # 16-byte Folded Reload
50-
; CHECK-NEXT: lxv 53, 144(1) # 16-byte Folded Reload
51-
; CHECK-NEXT: lxv 52, 128(1) # 16-byte Folded Reload
52-
; CHECK-NEXT: addi 1, 1, 320
28+
; CHECK-NEXT: addi 1, 1, 128
5329
; CHECK-NEXT: ld 0, 16(1)
5430
; CHECK-NEXT: mtlr 0
5531
; CHECK-NEXT: blr

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