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[AMDGPU] Avoid undefs in hazard-gfx1250-flat-scr-hi.mir. NFC
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-32
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+57
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‎llvm/test/CodeGen/AMDGPU/hazard-gfx1250-flat-scr-hi.mir‎

Lines changed: 57 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -8,10 +8,12 @@ body: |
88
bb.0:
99
1010
; GCN-LABEL: name: s_ashr_i64
11-
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
12-
; GCN-NEXT: [[S_ASHR_I64_:%[0-9]+]]:sreg_64 = S_ASHR_I64 undef %2:sreg_64, [[COPY]], implicit-def $scc
11+
; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
12+
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
13+
; GCN-NEXT: [[S_ASHR_I64_:%[0-9]+]]:sreg_64 = S_ASHR_I64 [[DEF]], [[COPY]], implicit-def $scc
14+
%1:sreg_64 = IMPLICIT_DEF
1315
%0:sreg_32 = COPY $src_flat_scratch_base_hi
14-
%2:sreg_64 = S_ASHR_I64 undef %1:sreg_64, %0, implicit-def $scc
16+
%2:sreg_64 = S_ASHR_I64 %1:sreg_64, %0, implicit-def $scc
1517
...
1618

1719
---
@@ -21,10 +23,12 @@ body: |
2123
bb.0:
2224
2325
; GCN-LABEL: name: s_lshl_b64
24-
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
25-
; GCN-NEXT: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 undef %2:sreg_64, [[COPY]], implicit-def $scc
26+
; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
27+
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
28+
; GCN-NEXT: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 [[DEF]], [[COPY]], implicit-def $scc
29+
%1:sreg_64 = IMPLICIT_DEF
2630
%0:sreg_32 = COPY $src_flat_scratch_base_hi
27-
%2:sreg_64 = S_LSHL_B64 undef %1:sreg_64, %0, implicit-def $scc
31+
%2:sreg_64 = S_LSHL_B64 %1:sreg_64, %0, implicit-def $scc
2832
...
2933

3034
---
@@ -34,10 +38,12 @@ body: |
3438
bb.0:
3539
3640
; GCN-LABEL: name: s_lshr_b64
37-
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
38-
; GCN-NEXT: [[S_LSHR_B64_:%[0-9]+]]:sreg_64 = S_LSHR_B64 undef %2:sreg_64, [[COPY]], implicit-def $scc
41+
; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
42+
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
43+
; GCN-NEXT: [[S_LSHR_B64_:%[0-9]+]]:sreg_64 = S_LSHR_B64 [[DEF]], [[COPY]], implicit-def $scc
44+
%1:sreg_64 = IMPLICIT_DEF
3945
%0:sreg_32 = COPY $src_flat_scratch_base_hi
40-
%2:sreg_64 = S_LSHR_B64 undef %1:sreg_64, %0, implicit-def $scc
46+
%2:sreg_64 = S_LSHR_B64 %1:sreg_64, %0, implicit-def $scc
4147
...
4248

4349
---
@@ -47,10 +53,12 @@ body: |
4753
bb.0:
4854
4955
; GCN-LABEL: name: s_bfe_i64
50-
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
51-
; GCN-NEXT: [[S_BFE_I64_:%[0-9]+]]:sreg_64 = S_BFE_I64 undef %2:sreg_64, [[COPY]], implicit-def $scc
56+
; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
57+
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
58+
; GCN-NEXT: [[S_BFE_I64_:%[0-9]+]]:sreg_64 = S_BFE_I64 [[DEF]], [[COPY]], implicit-def $scc
59+
%1:sreg_64 = IMPLICIT_DEF
5260
%0:sreg_32 = COPY $src_flat_scratch_base_hi
53-
%2:sreg_64 = S_BFE_I64 undef %1:sreg_64, %0, implicit-def $scc
61+
%2:sreg_64 = S_BFE_I64 %1:sreg_64, %0, implicit-def $scc
5462
...
5563

5664
---
@@ -60,10 +68,12 @@ body: |
6068
bb.0:
6169
6270
; GCN-LABEL: name: s_bfe_u64
63-
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
64-
; GCN-NEXT: [[S_BFE_U64_:%[0-9]+]]:sreg_64 = S_BFE_U64 undef %2:sreg_64, [[COPY]], implicit-def $scc
71+
; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
72+
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
73+
; GCN-NEXT: [[S_BFE_U64_:%[0-9]+]]:sreg_64 = S_BFE_U64 [[DEF]], [[COPY]], implicit-def $scc
74+
%1:sreg_64 = IMPLICIT_DEF
6575
%0:sreg_32 = COPY $src_flat_scratch_base_hi
66-
%2:sreg_64 = S_BFE_U64 undef %1:sreg_64, %0, implicit-def $scc
76+
%2:sreg_64 = S_BFE_U64 %1:sreg_64, %0, implicit-def $scc
6777
...
6878

6979
---
@@ -86,10 +96,14 @@ body: |
8696
bb.0:
8797
8898
; GCN-LABEL: name: s_bitcmp0_b64
89-
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
90-
; GCN-NEXT: S_BITCMP0_B64 undef %1:sreg_64, [[COPY]], implicit undef $scc, implicit-def $scc
99+
; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
100+
; GCN-NEXT: $scc = IMPLICIT_DEF
101+
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
102+
; GCN-NEXT: S_BITCMP0_B64 [[DEF]], [[COPY]], implicit $scc, implicit-def $scc
103+
%1:sreg_64 = IMPLICIT_DEF
104+
$scc = IMPLICIT_DEF
91105
%0:sreg_32 = COPY $src_flat_scratch_base_hi
92-
S_BITCMP0_B64 undef %1:sreg_64, %0, implicit undef $scc, implicit-def $scc
106+
S_BITCMP0_B64 %1:sreg_64, %0, implicit $scc, implicit-def $scc
93107
...
94108

95109
---
@@ -99,10 +113,14 @@ body: |
99113
bb.0:
100114
101115
; GCN-LABEL: name: s_bitcmp1_b64
102-
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
103-
; GCN-NEXT: S_BITCMP1_B64 undef %1:sreg_64, [[COPY]], implicit undef $scc, implicit-def $scc
116+
; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
117+
; GCN-NEXT: $scc = IMPLICIT_DEF
118+
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
119+
; GCN-NEXT: S_BITCMP1_B64 [[DEF]], [[COPY]], implicit $scc, implicit-def $scc
120+
%1:sreg_64 = IMPLICIT_DEF
121+
$scc = IMPLICIT_DEF
104122
%0:sreg_32 = COPY $src_flat_scratch_base_hi
105-
S_BITCMP1_B64 undef %1:sreg_64, %0, implicit undef $scc, implicit-def $scc
123+
S_BITCMP1_B64 %1:sreg_64, %0, implicit $scc, implicit-def $scc
106124
...
107125

108126
---
@@ -125,10 +143,12 @@ body: |
125143
bb.0:
126144
127145
; GCN-LABEL: name: s_bitset0_b64
128-
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
129-
; GCN-NEXT: [[S_BITSET0_B64_:%[0-9]+]]:sreg_64 = S_BITSET0_B64 [[COPY]], undef [[S_BITSET0_B64_]], implicit-def $scc
130-
%0:sreg_32 = COPY $src_flat_scratch_base_hi
131-
%1:sreg_64 = S_BITSET0_B64 %0, undef %1:sreg_64, implicit-def $scc
146+
; GCN: $sgpr0_sgpr1 = IMPLICIT_DEF
147+
; GCN-NEXT: $sgpr2 = S_MOV_B32 $src_flat_scratch_base_hi
148+
; GCN-NEXT: $sgpr0_sgpr1 = S_BITSET0_B64 $sgpr2, $sgpr0_sgpr1, implicit-def $scc
149+
$sgpr0_sgpr1 = IMPLICIT_DEF
150+
$sgpr2 = S_MOV_B32 $src_flat_scratch_base_hi
151+
$sgpr0_sgpr1 = S_BITSET0_B64 $sgpr2, $sgpr0_sgpr1, implicit-def $scc
132152
...
133153

134154
---
@@ -138,10 +158,12 @@ body: |
138158
bb.0:
139159
140160
; GCN-LABEL: name: s_bitset1_b64
141-
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
142-
; GCN-NEXT: [[S_BITSET1_B64_:%[0-9]+]]:sreg_64 = S_BITSET1_B64 [[COPY]], undef [[S_BITSET1_B64_]], implicit-def $scc
143-
%0:sreg_32 = COPY $src_flat_scratch_base_hi
144-
%1:sreg_64 = S_BITSET1_B64 %0, undef %1:sreg_64, implicit-def $scc
161+
; GCN: $sgpr0_sgpr1 = IMPLICIT_DEF
162+
; GCN-NEXT: $sgpr2 = S_MOV_B32 $src_flat_scratch_base_hi
163+
; GCN-NEXT: $sgpr0_sgpr1 = S_BITSET1_B64 $sgpr2, $sgpr0_sgpr1, implicit-def $scc
164+
$sgpr0_sgpr1 = IMPLICIT_DEF
165+
$sgpr2 = S_MOV_B32 $src_flat_scratch_base_hi
166+
$sgpr0_sgpr1 = S_BITSET1_B64 $sgpr2, $sgpr0_sgpr1, implicit-def $scc
145167
...
146168

147169
---
@@ -151,8 +173,11 @@ body: |
151173
bb.0:
152174
153175
; GCN-LABEL: name: s_ashr_i64_phys_dst
154-
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
155-
; GCN-NEXT: $sgpr0_sgpr1 = S_ASHR_I64 undef %1:sreg_64, [[COPY]], implicit-def $scc
176+
; GCN: $sgpr0_sgpr1 = IMPLICIT_DEF
177+
; GCN-NEXT: $sgpr2 = COPY $src_flat_scratch_base_hi
178+
; GCN-NEXT: $sgpr0_sgpr1 = S_ASHR_I64 $sgpr0_sgpr1, $sgpr2, implicit-def $scc
179+
$sgpr0_sgpr1 = IMPLICIT_DEF
180+
$sgpr2 = COPY $src_flat_scratch_base_hi
156181
%0:sreg_32 = COPY $src_flat_scratch_base_hi
157-
$sgpr0_sgpr1 = S_ASHR_I64 undef %1:sreg_64, %0, implicit-def $scc
182+
$sgpr0_sgpr1 = S_ASHR_I64 $sgpr0_sgpr1, $sgpr2, implicit-def $scc
158183
...

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