[x86 disassembler] AVX instructions in i386 mode mishandling vvvv field #11380
Description
| Bugzilla Link | 11008 |
| Resolution | FIXED |
| Resolved on | Nov 07, 2018 00:17 |
| Version | trunk |
| OS | All |
| Blocks | #11360 |
| Reporter | LLVM Bugzilla Contributor |
| CC | @topperc |
Extended Description
From the "Intel® 64 and IA-32 Architectures Software Developer’s Manual
Volume 2 (2A & 2B): Instruction Set Reference, A-Z", p. 2-21:
"In 32-bit mode the VEX first byte C4 and C5 alias onto the LES and LDS instructions. To maintain compatibility with existing programs the VEX 2nd byte, bits [7:6] must be 11b. To achieve this, the VEX payload bits are selected to place only inverted, 64-bit valid fields (extended register selectors) in these upper bits.
The 2-byte VEX Byte 1, bits [6:3] and the 3-byte VEX, Byte 2, bits [6:3] encode a field (shorthand VEX.vvvv) that for instructions with 2 or more source registers and an XMM or YMM or memory destination encodes the first source register specifier stored in inverted (1’s complement) form."
Testing with r140430, there are no problems disassembling this instruction in x86_64 mode:
$ echo '0xc5 0xf8 0x12 0x00'| ./llvm-mc -disassemble -triple="x86_64"
vmovlps (%rax), %xmm0, %xmm0
Change the vvvv field to alter the register source operand:
$ echo '0xc5 0xf0 0x12 0x00'| ./llvm-mc -disassemble -triple="x86_64"
vmovlps (%rax), %xmm1, %xmm0
In i386 mode, things work with the vvvv field set to 1111b:
$ echo '0xc5 0xf8 0x12 0x00'| ./llvm-mc -disassemble -triple="i386"
vmovlps (%eax), %xmm0, %xmm0
But if you try to change the vvvv field:
$ echo '0xc5 0xf0 0x12 0x00'| ./llvm-mc -disassemble -triple="i386"
:1:1: warning: invalid instruction encoding
0xc5 0xf0 0x12 0x00
^
adcb (%eax), %al