[DAG] MatchLoadCombine - match swapped loads

[RKSimon]

Sort of an extension to the BSWAP pattern code:

uint64_t ll(uint32_t *p) {
    uint64_t h = *p++;
    h <<= 32;
    h |= *p++;
    return h;
}

ll:
        movl    (%rdi), %ecx
        movl    4(%rdi), %eax
        shlq    $32, %rcx
        orq     %rcx, %rax
        retq

These i32 loads are swapped preventing them being combined into a single i64 load.

But assuming we can cheaply rotate them then we can load the i64 and then rotate it:

uint64_t rr(uint32_t *p) {
    uint64_t h = *p++;
    h |= (uint64_t)*p++ << 32;
    return __builtin_rotateright64(h, 32);
}

rr:
        rorxq   $32, (%rdi), %rax
        retq

define i64 @src(ptr %p) {
  %p.hi = getelementptr inbounds nuw i8, ptr %p, i64 4
  %lo = load i32, ptr %p
  %hi = load i32, ptr %p.hi
  %conv = zext i32 %lo to i64
  %shl = shl nuw i64 %conv, 32
  %conv2 = zext i32 %hi to i64
  %or = or disjoint i64 %shl, %conv2
  ret i64 %or
}

define i64 @tgt(ptr %p) {
  %p.hi = getelementptr inbounds nuw i8, ptr %p, i64 4
  %lo = load i32, ptr %p
  %hi = load i32, ptr %p.hi
  %conv = zext i32 %hi to i64
  %shl = shl nuw i64 %conv, 32
  %conv2 = zext i32 %lo to i64
  %or = or disjoint i64 %shl, %conv2
  %rot = tail call i64 @llvm.fshl.i64(i64 %or, i64 %or, i64 32)
  ret i64 %rot
}
declare i64 @llvm.fshl.i64(i64, i64, i64) #1

[llvmbot]

Hi!

This issue may be a good introductory issue for people new to working on LLVM. If you would like to work on this issue, your first steps are:

1. Check that no other contributor is working on this issue. If someone is assigned to the issue or claimed to be working on it, ping the person. After one week without a response, the assignee may be changed.
2. Leave a comment indicating that you are working on the issue, or just create a pull request after following the steps below. Mention this issue in the description of the pull request.
3. Fix the issue locally.
4. Run the test suite locally. Remember that the subdirectories under test/ create fine-grained testing targets, so you can e.g. use make check-clang-ast to only run Clang's AST tests.
5. Create a Git commit.
6. Run git clang-format HEAD~1 to format your changes.
7. Open a pull request to the upstream repository on GitHub. Detailed instructions can be found in GitHub's documentation. Mention this issue in the description of the pull request.

If you have any further questions about this issue, don't hesitate to ask via a comment in the thread below.

[llvmbot]

@llvm/issue-subscribers-good-first-issue

Author: Simon Pilgrim (RKSimon)

Sort of an extension to the BSWAP pattern code:

uint64_t ll(uint32_t *p) {
    uint64_t h = *p++;
    h <<= 32;
    h |= *p++;
    return h;
}

ll:
        movl    (%rdi), %ecx
        movl    4(%rdi), %eax
        shlq    $32, %rcx
        orq     %rcx, %rax
        retq

These i32 loads are swapped preventing them being combined into a single i64 load.

But assuming we can cheaply rotate them then we can load the i64 and then rotate it:

uint64_t rr(uint32_t *p) {
    uint64_t h = *p++;
    h |= (uint64_t)*p++ << 32;
    return __builtin_rotateright64(h, 32);
}

rr:
        rorxq   $32, (%rdi), %rax
        retq

define i64 @<!-- -->src(ptr %p) {
  %p.hi = getelementptr inbounds nuw i8, ptr %p, i64 4
  %lo = load i32, ptr %p
  %hi = load i32, ptr %p.hi
  %conv = zext i32 %lo to i64
  %shl = shl nuw i64 %conv, 32
  %conv2 = zext i32 %hi to i64
  %or = or disjoint i64 %shl, %conv2
  ret i64 %or
}

define i64 @<!-- -->tgt(ptr %p) {
  %p.hi = getelementptr inbounds nuw i8, ptr %p, i64 4
  %lo = load i32, ptr %p
  %hi = load i32, ptr %p.hi
  %conv = zext i32 %hi to i64
  %shl = shl nuw i64 %conv, 32
  %conv2 = zext i32 %lo to i64
  %or = or disjoint i64 %shl, %conv2
  %rot = tail call i64 @<!-- -->llvm.fshl.i64(i64 %or, i64 %or, i64 32)
  ret i64 %rot
}
declare i64 @<!-- -->llvm.fshl.i64(i64, i64, i64) #<!-- -->1

[GrumpyPigSkin]

@RKSimon I'd like to work on this :)