[clang][X86] VectorExprEvaluator::VisitCallExpr / InterpretBuiltin - allow VALIGND/Q element shift intrinsics to be used in constexpr

[RKSimon]

__m128i _mm_alignr_epi32 (__m128i a, __m128i b, const int imm8)
__m128i _mm_mask_alignr_epi32 (__m128i src, __mmask8 k, __m128i a, __m128i b, const int imm8)
__m128i _mm_maskz_alignr_epi32 (__mmask8 k, __m128i a, __m128i b, const int imm8)
__m256i _mm256_alignr_epi32 (__m256i a, __m256i b, const int imm8)
__m256i _mm256_mask_alignr_epi32 (__m256i src, __mmask8 k, __m256i a, __m256i b, const int imm8)
__m256i _mm256_maskz_alignr_epi32 (__mmask8 k, __m256i a, __m256i b, const int imm8)
__m512i _mm512_alignr_epi32 (__m512i a, __m512i b, const int imm8)
__m512i _mm512_mask_alignr_epi32 (__m512i src, __mmask16 k, __m512i a, __m512i b, const int imm8)
__m512i _mm512_maskz_alignr_epi32 (__mmask16 k, __m512i a, __m512i b, const int imm8)

__m128i _mm_alignr_epi64 (__m128i a, __m128i b, const int imm8)
__m128i _mm_mask_alignr_epi64 (__m128i src, __mmask8 k, __m128i a, __m128i b, const int imm8)
__m128i _mm_maskz_alignr_epi64 (__mmask8 k, __m128i a, __m128i b, const int imm8)
__m256i _mm256_alignr_epi64 (__m256i a, __m256i b, const int imm8)
__m256i _mm256_mask_alignr_epi64 (__m256i src, __mmask8 k, __m256i a, __m256i b, const int imm8)
__m256i _mm256_maskz_alignr_epi64 (__mmask8 k, __m256i a, __m256i b, const int imm8)
__m512i _mm512_alignr_epi64 (__m512i a, __m512i b, const int imm8)
__m512i _mm512_mask_alignr_epi64 (__m512i src, __mmask8 k, __m512i a, __m512i b, const int imm8)
__m512i _mm512_maskz_alignr_epi64 (__mmask8 k, __m512i a, __m512i b, const int imm8)

Unlike many shuffles (inc PALIGNR) - these are act across the full vector width - review CodeGenFunction::EmitX86BuiltinExpr to see how they can be implemented - should still be able to use a interp__builtin_ia32_shuffle_generic/evalShuffleGeneric callback however

[llvmbot]

@llvm/issue-subscribers-backend-x86

Author: Simon Pilgrim (RKSimon)

``` __m128i _mm_alignr_epi32 (__m128i a, __m128i b, const int imm8) __m128i _mm_mask_alignr_epi32 (__m128i src, __mmask8 k, __m128i a, __m128i b, const int imm8) __m128i _mm_maskz_alignr_epi32 (__mmask8 k, __m128i a, __m128i b, const int imm8) __m256i _mm256_alignr_epi32 (__m256i a, __m256i b, const int imm8) __m256i _mm256_mask_alignr_epi32 (__m256i src, __mmask8 k, __m256i a, __m256i b, const int imm8) __m256i _mm256_maskz_alignr_epi32 (__mmask8 k, __m256i a, __m256i b, const int imm8) __m512i _mm512_alignr_epi32 (__m512i a, __m512i b, const int imm8) __m512i _mm512_mask_alignr_epi32 (__m512i src, __mmask16 k, __m512i a, __m512i b, const int imm8) __m512i _mm512_maskz_alignr_epi32 (__mmask16 k, __m512i a, __m512i b, const int imm8)

__m128i _mm_alignr_epi64 (__m128i a, __m128i b, const int imm8)
__m128i _mm_mask_alignr_epi64 (__m128i src, __mmask8 k, __m128i a, __m128i b, const int imm8)
__m128i _mm_maskz_alignr_epi64 (__mmask8 k, __m128i a, __m128i b, const int imm8)
__m256i _mm256_alignr_epi64 (__m256i a, __m256i b, const int imm8)
__m256i _mm256_mask_alignr_epi64 (__m256i src, __mmask8 k, __m256i a, __m256i b, const int imm8)
__m256i _mm256_maskz_alignr_epi64 (__mmask8 k, __m256i a, __m256i b, const int imm8)
__m512i _mm512_alignr_epi64 (__m512i a, __m512i b, const int imm8)
__m512i _mm512_mask_alignr_epi64 (__m512i src, __mmask8 k, __m512i a, __m512i b, const int imm8)
__m512i _mm512_maskz_alignr_epi64 (__mmask8 k, __m512i a, __m512i b, const int imm8)

Unlike many shuffles (inc PALIGNR) - these are act across the full vector width - review CodeGenFunction::EmitX86BuiltinExpr to see how they can be implemented - should still be able to use a interp__builtin_ia32_shuffle_generic/evalShuffleGeneric callback however
</details>

[llvmbot]

Hi!

This issue may be a good introductory issue for people new to working on LLVM. If you would like to work on this issue, your first steps are:

1. Check that no other contributor is working on this issue. If someone is assigned to the issue or claimed to be working on it, ping the person. After one week without a response, the assignee may be changed.
2. Leave a comment indicating that you are working on the issue, or just create a pull request after following the steps below. Mention this issue in the description of the pull request.
3. Fix the issue locally.
4. Run the test suite locally. Remember that the subdirectories under test/ create fine-grained testing targets, so you can e.g. use make check-clang-ast to only run Clang's AST tests.
5. Create a Git commit.
6. Run git clang-format HEAD~1 to format your changes.
7. Open a pull request to the upstream repository on GitHub. Detailed instructions can be found in GitHub's documentation. Mention this issue in the description of the pull request.

If you have any further questions about this issue, don't hesitate to ask via a comment in the thread below.

[llvmbot]

@llvm/issue-subscribers-good-first-issue

Author: Simon Pilgrim (RKSimon)

``` __m128i _mm_alignr_epi32 (__m128i a, __m128i b, const int imm8) __m128i _mm_mask_alignr_epi32 (__m128i src, __mmask8 k, __m128i a, __m128i b, const int imm8) __m128i _mm_maskz_alignr_epi32 (__mmask8 k, __m128i a, __m128i b, const int imm8) __m256i _mm256_alignr_epi32 (__m256i a, __m256i b, const int imm8) __m256i _mm256_mask_alignr_epi32 (__m256i src, __mmask8 k, __m256i a, __m256i b, const int imm8) __m256i _mm256_maskz_alignr_epi32 (__mmask8 k, __m256i a, __m256i b, const int imm8) __m512i _mm512_alignr_epi32 (__m512i a, __m512i b, const int imm8) __m512i _mm512_mask_alignr_epi32 (__m512i src, __mmask16 k, __m512i a, __m512i b, const int imm8) __m512i _mm512_maskz_alignr_epi32 (__mmask16 k, __m512i a, __m512i b, const int imm8)

__m128i _mm_alignr_epi64 (__m128i a, __m128i b, const int imm8)
__m128i _mm_mask_alignr_epi64 (__m128i src, __mmask8 k, __m128i a, __m128i b, const int imm8)
__m128i _mm_maskz_alignr_epi64 (__mmask8 k, __m128i a, __m128i b, const int imm8)
__m256i _mm256_alignr_epi64 (__m256i a, __m256i b, const int imm8)
__m256i _mm256_mask_alignr_epi64 (__m256i src, __mmask8 k, __m256i a, __m256i b, const int imm8)
__m256i _mm256_maskz_alignr_epi64 (__mmask8 k, __m256i a, __m256i b, const int imm8)
__m512i _mm512_alignr_epi64 (__m512i a, __m512i b, const int imm8)
__m512i _mm512_mask_alignr_epi64 (__m512i src, __mmask8 k, __m512i a, __m512i b, const int imm8)
__m512i _mm512_maskz_alignr_epi64 (__mmask8 k, __m512i a, __m512i b, const int imm8)

Unlike many shuffles (inc PALIGNR) - these are act across the full vector width - review CodeGenFunction::EmitX86BuiltinExpr to see how they can be implemented - should still be able to use a interp__builtin_ia32_shuffle_generic/evalShuffleGeneric callback however
</details>

[Priyanshu3820]

Hi! I would like to work on this issue. Please assign this to me.

[0xzre]

it seems like the VALIGND/Q family should be handled similarly to __builtin_ia32_palignr*, just without the per-lane restriction?