Machine verifier failure in CodeGen/AArch64/alias_mask.ll

[AZero13]

After #167527 (commit e5baf07), running ninja check-llvm-codegen-aarch64 fails with:

# Machine code for function whilewr_8_scalarize: IsSSA, TracksLiveness
...
  CCMPXr %2:gpr64common, 0, 4, 13, implicit-def $nzcv, implicit $nzcv
  %4:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
...

*** Bad machine code: Expected a register operand. ***
- function:    whilewr_8_scalarize
- basic block: %bb.0 entry (0x109034d18)
- instruction: CCMPXr %2:gpr64common, 0, 4, 13, implicit-def $nzcv, implicit $nzcv
- operand 1:   0
LLVM ERROR: Found 1 machine code errors.```

This happens with the LLVM IR:
```define <1 x i1> @whilewr_8_scalarize(ptr %a, ptr %b) {
; CHECK-LABEL: whilewr_8_scalarize:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    sub x8, x1, x0
; CHECK-NEXT:    cmp x8, #0
; CHECK-NEXT:    ccmp x8, #0, #4, le
; CHECK-NEXT:    cset w0, eq
; CHECK-NEXT:    ret
entry:
  %0 = call <1 x i1> @llvm.loop.dependence.war.mask.v1i1(ptr %a, ptr %b, i64 1)
  ret <1 x i1> %0
}

TargetConstant nodes don't match TableGen ImmLeaf patterns during instruction selection
When the zero constant flows into CCMP formation, the pattern matcher cannot match CCMPXi (immediate form) because the imm0_31 predicate only matches regular Constant nodes.