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[DAGCombiner] Add pattern matching for negated subtraction in ABDU selection #156217

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[DAGCombiner] Add pattern matching for negated subtraction in ABDU selection #156217

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Pre-commit test (NFC)
AZero13 Aug 31, 2025
c61539c
[DAGCombiner] Add pattern matching for negated subtraction in ABDU se…
AZero13 Aug 31, 2025
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50 changes: 34 additions & 16 deletions llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -12284,27 +12284,45 @@ SDValue DAGCombiner::foldSelectToABD(SDValue LHS, SDValue RHS, SDValue True,
case ISD::SETGT:
case ISD::SETGE:
case ISD::SETUGT:
case ISD::SETUGE:
if (sd_match(True, m_Sub(m_Specific(LHS), m_Specific(RHS))) &&
sd_match(False, m_Sub(m_Specific(RHS), m_Specific(LHS))))
return DAG.getNode(ABDOpc, DL, VT, LHS, RHS);
if (sd_match(True, m_Sub(m_Specific(RHS), m_Specific(LHS))) &&
sd_match(False, m_Sub(m_Specific(LHS), m_Specific(RHS))) &&
hasOperation(ABDOpc, VT))
return DAG.getNegative(DAG.getNode(ABDOpc, DL, VT, LHS, RHS), DL, VT);
case ISD::SETUGE: {
if (sd_match(True, m_Sub(m_Specific(LHS), m_Specific(RHS)))) {
if (sd_match(False, m_Sub(m_Specific(RHS), m_Specific(LHS))))
return DAG.getNode(ABDOpc, DL, VT, LHS, RHS);

if (sd_match(False, m_Neg(m_Sub(m_Specific(LHS), m_Specific(RHS)))))
return DAG.getNode(ABDOpc, DL, VT, LHS, RHS);
}

if (sd_match(True, m_Sub(m_Specific(RHS), m_Specific(LHS)))) {
if (sd_match(False, m_Sub(m_Specific(LHS), m_Specific(RHS))))
return DAG.getNegative(DAG.getNode(ABDOpc, DL, VT, LHS, RHS), DL, VT);

if (sd_match(False, m_Neg(m_Sub(m_Specific(RHS), m_Specific(LHS)))))
return DAG.getNegative(DAG.getNode(ABDOpc, DL, VT, LHS, RHS), DL, VT);
}
break;
}
case ISD::SETLT:
case ISD::SETLE:
case ISD::SETULT:
case ISD::SETULE:
if (sd_match(True, m_Sub(m_Specific(RHS), m_Specific(LHS))) &&
sd_match(False, m_Sub(m_Specific(LHS), m_Specific(RHS))))
return DAG.getNode(ABDOpc, DL, VT, LHS, RHS);
if (sd_match(True, m_Sub(m_Specific(LHS), m_Specific(RHS))) &&
sd_match(False, m_Sub(m_Specific(RHS), m_Specific(LHS))) &&
hasOperation(ABDOpc, VT))
return DAG.getNegative(DAG.getNode(ABDOpc, DL, VT, LHS, RHS), DL, VT);
case ISD::SETULE: {
if (sd_match(True, m_Sub(m_Specific(RHS), m_Specific(LHS)))) {
if (sd_match(False, m_Sub(m_Specific(LHS), m_Specific(RHS))))
return DAG.getNode(ABDOpc, DL, VT, LHS, RHS);

if (sd_match(False, m_Neg(m_Sub(m_Specific(RHS), m_Specific(LHS)))))
return DAG.getNode(ABDOpc, DL, VT, LHS, RHS);
}

if (sd_match(True, m_Sub(m_Specific(LHS), m_Specific(RHS)))) {
if (sd_match(False, m_Sub(m_Specific(RHS), m_Specific(LHS))))
return DAG.getNegative(DAG.getNode(ABDOpc, DL, VT, LHS, RHS), DL, VT);

if (sd_match(False, m_Neg(m_Sub(m_Specific(LHS), m_Specific(RHS)))))
return DAG.getNegative(DAG.getNode(ABDOpc, DL, VT, LHS, RHS), DL, VT);
}
break;
}
default:
break;
}
Expand Down
30 changes: 14 additions & 16 deletions llvm/test/CodeGen/AArch64/abds-neg.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -310,10 +310,8 @@ define i8 @abd_cmp_i8(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: abd_cmp_i8:
; CHECK: // %bb.0:
; CHECK-NEXT: sxtb w8, w0
; CHECK-NEXT: sub w9, w0, w1
; CHECK-NEXT: sub w10, w1, w0
; CHECK-NEXT: cmp w8, w1, sxtb
; CHECK-NEXT: csel w0, w9, w10, le
; CHECK-NEXT: subs w8, w8, w1, sxtb
; CHECK-NEXT: cneg w0, w8, pl
; CHECK-NEXT: ret
%cmp = icmp sle i8 %a, %b
%ab = sub i8 %a, %b
Expand All @@ -326,10 +324,8 @@ define i16 @abd_cmp_i16(i16 %a, i16 %b) nounwind {
; CHECK-LABEL: abd_cmp_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: sxth w8, w0
; CHECK-NEXT: sub w9, w0, w1
; CHECK-NEXT: sub w10, w1, w0
; CHECK-NEXT: cmp w8, w1, sxth
; CHECK-NEXT: csel w0, w9, w10, lt
; CHECK-NEXT: subs w8, w8, w1, sxth
; CHECK-NEXT: cneg w0, w8, pl
; CHECK-NEXT: ret
%cmp = icmp slt i16 %a, %b
%ab = sub i16 %a, %b
Expand All @@ -342,7 +338,7 @@ define i32 @abd_cmp_i32(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: abd_cmp_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: subs w8, w0, w1
; CHECK-NEXT: cneg w0, w8, ge
; CHECK-NEXT: cneg w0, w8, gt
; CHECK-NEXT: ret
%cmp = icmp sge i32 %a, %b
%ab = sub i32 %a, %b
Expand All @@ -355,7 +351,7 @@ define i64 @abd_cmp_i64(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: abd_cmp_i64:
; CHECK: // %bb.0:
; CHECK-NEXT: subs x8, x0, x1
; CHECK-NEXT: cneg x0, x8, ge
; CHECK-NEXT: cneg x0, x8, gt
; CHECK-NEXT: ret
%cmp = icmp slt i64 %a, %b
%ab = sub i64 %a, %b
Expand All @@ -367,12 +363,14 @@ define i64 @abd_cmp_i64(i64 %a, i64 %b) nounwind {
define i128 @abd_cmp_i128(i128 %a, i128 %b) nounwind {
; CHECK-LABEL: abd_cmp_i128:
; CHECK: // %bb.0:
; CHECK-NEXT: subs x8, x2, x0
; CHECK-NEXT: sbc x9, x3, x1
; CHECK-NEXT: subs x10, x0, x2
; CHECK-NEXT: sbcs x11, x1, x3
; CHECK-NEXT: csel x0, x10, x8, lt
; CHECK-NEXT: csel x1, x11, x9, lt
; CHECK-NEXT: subs x8, x0, x2
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This looks worse?

; CHECK-NEXT: sbc x9, x1, x3
; CHECK-NEXT: subs x10, x2, x0
; CHECK-NEXT: sbcs x11, x3, x1
; CHECK-NEXT: csel x8, x8, x10, lt
; CHECK-NEXT: csel x9, x9, x11, lt
; CHECK-NEXT: negs x0, x8
; CHECK-NEXT: ngc x1, x9
; CHECK-NEXT: ret
%cmp = icmp slt i128 %a, %b
%ab = sub i128 %a, %b
Expand Down
30 changes: 14 additions & 16 deletions llvm/test/CodeGen/AArch64/abdu-neg.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -310,10 +310,8 @@ define i8 @abd_cmp_i8(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: abd_cmp_i8:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xff
; CHECK-NEXT: sub w9, w0, w1
; CHECK-NEXT: sub w10, w1, w0
; CHECK-NEXT: cmp w8, w1, uxtb
; CHECK-NEXT: csel w0, w9, w10, ls
; CHECK-NEXT: subs w8, w8, w1, uxtb
; CHECK-NEXT: cneg w0, w8, pl
; CHECK-NEXT: ret
%cmp = icmp ule i8 %a, %b
%ab = sub i8 %a, %b
Expand All @@ -326,10 +324,8 @@ define i16 @abd_cmp_i16(i16 %a, i16 %b) nounwind {
; CHECK-LABEL: abd_cmp_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0xffff
; CHECK-NEXT: sub w9, w0, w1
; CHECK-NEXT: sub w10, w1, w0
; CHECK-NEXT: cmp w8, w1, uxth
; CHECK-NEXT: csel w0, w9, w10, lo
; CHECK-NEXT: subs w8, w8, w1, uxth
; CHECK-NEXT: cneg w0, w8, pl
; CHECK-NEXT: ret
%cmp = icmp ult i16 %a, %b
%ab = sub i16 %a, %b
Expand All @@ -342,7 +338,7 @@ define i32 @abd_cmp_i32(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: abd_cmp_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: subs w8, w0, w1
; CHECK-NEXT: cneg w0, w8, hs
; CHECK-NEXT: cneg w0, w8, hi
; CHECK-NEXT: ret
%cmp = icmp uge i32 %a, %b
%ab = sub i32 %a, %b
Expand All @@ -355,7 +351,7 @@ define i64 @abd_cmp_i64(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: abd_cmp_i64:
; CHECK: // %bb.0:
; CHECK-NEXT: subs x8, x0, x1
; CHECK-NEXT: cneg x0, x8, hs
; CHECK-NEXT: cneg x0, x8, hi
; CHECK-NEXT: ret
%cmp = icmp ult i64 %a, %b
%ab = sub i64 %a, %b
Expand All @@ -367,12 +363,14 @@ define i64 @abd_cmp_i64(i64 %a, i64 %b) nounwind {
define i128 @abd_cmp_i128(i128 %a, i128 %b) nounwind {
; CHECK-LABEL: abd_cmp_i128:
; CHECK: // %bb.0:
; CHECK-NEXT: subs x8, x2, x0
; CHECK-NEXT: sbc x9, x3, x1
; CHECK-NEXT: subs x10, x0, x2
; CHECK-NEXT: sbcs x11, x1, x3
; CHECK-NEXT: csel x0, x10, x8, lo
; CHECK-NEXT: csel x1, x11, x9, lo
; CHECK-NEXT: subs x8, x0, x2
; CHECK-NEXT: sbc x9, x1, x3
; CHECK-NEXT: subs x10, x2, x0
; CHECK-NEXT: sbcs x11, x3, x1
; CHECK-NEXT: csel x8, x8, x10, lo
; CHECK-NEXT: csel x9, x9, x11, lo
; CHECK-NEXT: negs x0, x8
; CHECK-NEXT: ngc x1, x9
; CHECK-NEXT: ret
%cmp = icmp ult i128 %a, %b
%ab = sub i128 %a, %b
Expand Down
7 changes: 3 additions & 4 deletions llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll
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Expand Up @@ -966,10 +966,9 @@ define <4 x i32> @absd_int32_ugt_opp(<4 x i32>, <4 x i32>) {
;
; CHECK-PWR78-LABEL: absd_int32_ugt_opp:
; CHECK-PWR78: # %bb.0:
; CHECK-PWR78-NEXT: vcmpgtuw v4, v2, v3
; CHECK-PWR78-NEXT: vsubuwm v5, v2, v3
; CHECK-PWR78-NEXT: vsubuwm v2, v3, v2
; CHECK-PWR78-NEXT: xxsel v2, v5, v2, v4
; CHECK-PWR78-NEXT: vmaxuw v4, v2, v3
; CHECK-PWR78-NEXT: vminuw v2, v2, v3
; CHECK-PWR78-NEXT: vsubuwm v2, v2, v4
; CHECK-PWR78-NEXT: blr
%3 = icmp ugt <4 x i32> %0, %1
%4 = sub <4 x i32> %0, %1
Expand Down
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