[PowerPC][NFC] Apply clang-format to PPCInstrFuture.td #157135
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@llvm/pr-subscribers-backend-powerpc Author: Lei Huang (lei137) ChangesFull diff: https://github.com/llvm/llvm-project/pull/157135.diff 1 Files Affected:
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
index 8cf5c850ad481..a12dfae2a0d7f 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
@@ -13,7 +13,7 @@
class XOForm_RTAB5_L1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
string asmstr, list<dag> pattern>
- : I<opcode, OOL, IOL, asmstr, NoItinerary> {
+ : I<opcode, OOL, IOL, asmstr, NoItinerary> {
bits<5> RT;
bits<5> RA;
bits<5> RB;
@@ -21,27 +21,27 @@ class XOForm_RTAB5_L1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
let Pattern = pattern;
- bit RC = 0; // set by isRecordForm
+ bit RC = 0; // set by isRecordForm
- let Inst{6...10} = RT;
+ let Inst{6...10} = RT;
let Inst{11...15} = RA;
let Inst{16...20} = RB;
- let Inst{21} = L;
+ let Inst{21} = L;
let Inst{22...30} = xo;
- let Inst{31} = RC;
+ let Inst{31} = RC;
}
multiclass XOForm_RTAB5_L1r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
- string asmbase, string asmstr,
- list<dag> pattern> {
+ string asmbase, string asmstr, list<dag> pattern> {
let BaseName = asmbase in {
def NAME : XOForm_RTAB5_L1<opcode, xo, OOL, IOL,
!strconcat(asmbase, !strconcat(" ", asmstr)),
- pattern>, RecFormRel;
- let Defs = [CR0] in
- def _rec : XOForm_RTAB5_L1<opcode, xo, OOL, IOL,
- !strconcat(asmbase, !strconcat(". ", asmstr)),
- []>, isRecordForm, RecFormRel;
+ pattern>,
+ RecFormRel;
+ let Defs = [CR0] in def _rec
+ : XOForm_RTAB5_L1<opcode, xo, OOL, IOL,
+ !strconcat(asmbase, !strconcat(". ", asmstr)), []>,
+ isRecordForm, RecFormRel;
}
}
@@ -122,39 +122,40 @@ class VXForm_VRTAB5<bits<11> xo, dag OOL, dag IOL, string asmstr,
let Predicates = [IsISAFuture] in {
defm SUBFUS : XOForm_RTAB5_L1r<31, 72, (outs g8rc:$RT),
- (ins g8rc:$RA, g8rc:$RB, u1imm:$L),
- "subfus", "$RT, $L, $RA, $RB", []>;
+ (ins g8rc:$RA, g8rc:$RB, u1imm:$L), "subfus",
+ "$RT, $L, $RA, $RB", []>;
}
let Predicates = [HasVSX, IsISAFuture] in {
let mayLoad = 1 in {
- def LXVRL
- : XX1Form_memOp<31, 525, (outs vsrc:$XT), (ins (memr $RA):$addr, g8rc:$RB),
- "lxvrl $XT, $addr, $RB", IIC_LdStLoad, []>;
- def LXVRLL
- : XX1Form_memOp<31, 557, (outs vsrc:$XT), (ins (memr $RA):$addr, g8rc:$RB),
- "lxvrll $XT, $addr, $RB", IIC_LdStLoad, []>;
- def LXVPRL
- : XForm_XTp5_XAB5<31, 589, (outs vsrprc:$XTp), (ins (memr $RA):$addr, g8rc:$RB),
- "lxvprl $XTp, $addr, $RB", IIC_LdStLFD, []>;
- def LXVPRLL
- : XForm_XTp5_XAB5<31, 621, (outs vsrprc:$XTp), (ins (memr $RA):$addr, g8rc:$RB),
- "lxvprll $XTp, $addr, $RB", IIC_LdStLFD, []>;
+ def LXVRL : XX1Form_memOp<31, 525, (outs vsrc:$XT),
+ (ins (memr $RA):$addr, g8rc:$RB),
+ "lxvrl $XT, $addr, $RB", IIC_LdStLoad, []>;
+ def LXVRLL : XX1Form_memOp<31, 557, (outs vsrc:$XT),
+ (ins (memr $RA):$addr, g8rc:$RB),
+ "lxvrll $XT, $addr, $RB", IIC_LdStLoad, []>;
+ def LXVPRL : XForm_XTp5_XAB5<31, 589, (outs vsrprc:$XTp),
+ (ins (memr $RA):$addr, g8rc:$RB),
+ "lxvprl $XTp, $addr, $RB", IIC_LdStLFD, []>;
+ def LXVPRLL : XForm_XTp5_XAB5<31, 621, (outs vsrprc:$XTp),
+ (ins (memr $RA):$addr, g8rc:$RB),
+ "lxvprll $XTp, $addr, $RB", IIC_LdStLFD, []>;
}
let mayStore = 1 in {
- def STXVRL
- : XX1Form_memOp<31, 653, (outs), (ins vsrc:$XT, (memr $RA):$addr, g8rc:$RB),
- "stxvrl $XT, $addr, $RB", IIC_LdStLoad, []>;
- def STXVRLL
- : XX1Form_memOp<31, 685, (outs), (ins vsrc:$XT, (memr $RA):$addr, g8rc:$RB),
- "stxvrll $XT, $addr, $RB", IIC_LdStLoad, []>;
+ def STXVRL : XX1Form_memOp<31, 653, (outs),
+ (ins vsrc:$XT, (memr $RA):$addr, g8rc:$RB),
+ "stxvrl $XT, $addr, $RB", IIC_LdStLoad, []>;
+ def STXVRLL : XX1Form_memOp<31, 685, (outs),
+ (ins vsrc:$XT, (memr $RA):$addr, g8rc:$RB),
+ "stxvrll $XT, $addr, $RB", IIC_LdStLoad, []>;
def STXVPRL : XForm_XTp5_XAB5<31, 717, (outs),
(ins vsrprc:$XTp, (memr $RA):$addr, g8rc:$RB),
"stxvprl $XTp, $addr, $RB", IIC_LdStLFD, []>;
- def STXVPRLL : XForm_XTp5_XAB5<31, 749, (outs),
- (ins vsrprc:$XTp, (memr $RA):$addr, g8rc:$RB),
- "stxvprll $XTp, $addr, $RB", IIC_LdStLFD, []>;
+ def STXVPRLL
+ : XForm_XTp5_XAB5<31, 749, (outs),
+ (ins vsrprc:$XTp, (memr $RA):$addr, g8rc:$RB),
+ "stxvprll $XTp, $addr, $RB", IIC_LdStLFD, []>;
}
def VUPKHSNTOB : VXForm_VRTB5<387, 0, (outs vrrc:$VRT), (ins vrrc:$VRB),
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/181/builds/27353 Here is the relevant piece of the build log for the reference |
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