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Fix some typos in machine verifier comments and trace output #160049

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Merged
merged 3 commits into from
Sep 29, 2025
Merged

Fix some typos in machine verifier comments and trace output #160049

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901a9b3
Fix some typos in machine verifier comments and trace output
danstadelmann Sep 22, 2025
c353c76
fixup! Fix some typos in machine verifier comments and trace output
danstadelmann Sep 29, 2025
38af932
Merge branch 'main' into main
danstadelmann Sep 29, 2025
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20 changes: 10 additions & 10 deletions llvm/lib/CodeGen/MachineVerifier.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1549,7 +1549,7 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
report("G_BUILD_VECTOR result element type must match source type", MI);

if (DstTy.getNumElements() != MI->getNumOperands() - 1)
report("G_BUILD_VECTOR must have an operand for each elemement", MI);
report("G_BUILD_VECTOR must have an operand for each element", MI);

for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 2))
if (MRI->getType(MI->getOperand(1).getReg()) != MRI->getType(MO.getReg()))
Expand Down Expand Up @@ -2398,11 +2398,11 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {

// The next two checks allow COPY between physical and virtual registers,
// when the virtual register has a scalable size and the physical register
// has a fixed size. These checks allow COPY between *potentialy* mismatched
// sizes. However, once RegisterBankSelection occurs, MachineVerifier should
// be able to resolve a fixed size for the scalable vector, and at that
// point this function will know for sure whether the sizes are mismatched
// and correctly report a size mismatch.
// has a fixed size. These checks allow COPY between *potentially*
// mismatched sizes. However, once RegisterBankSelection occurs,
// MachineVerifier should be able to resolve a fixed size for the scalable
// vector, and at that point this function will know for sure whether the
// sizes are mismatched and correctly report a size mismatch.
if (SrcReg.isPhysical() && DstReg.isVirtual() && DstSize.isScalable() &&
!SrcSize.isScalable())
break;
Expand Down Expand Up @@ -3213,13 +3213,13 @@ struct VRegFilter {

private:
static constexpr unsigned SparseUniverseMax = 10 * 1024 * 8;
// VRegs indexed within SparseUniverseMax are tracked by Sparse, those beyound
// are tracked by Dense. The only purpose of the threashold and the Dense set
// VRegs indexed within SparseUniverseMax are tracked by Sparse, those beyond
// are tracked by Dense. The only purpose of the threshold and the Dense set
// is to have a reasonably growing memory usage in pathological cases (large
// number of very sparse VRegFilter instances live at the same time). In
// practice even in the worst-by-execution time cases having all elements
// tracked by Sparse (very large SparseUniverseMax scenario) tends to be more
// space efficient than if tracked by Dense. The threashold is set to keep the
// space efficient than if tracked by Dense. The threshold is set to keep the
// worst-case memory usage within 2x of figures determined empirically for
// "all Dense" scenario in such worst-by-execution-time cases.
BitVector Sparse;
Expand Down Expand Up @@ -3459,7 +3459,7 @@ void MachineVerifier::visitMachineFunctionAfter() {

// Check live-in list of each MBB. If a register is live into MBB, check
// that the register is in regsLiveOut of each predecessor block. Since
// this must come from a definition in the predecesssor or its live-in
// this must come from a definition in the predecessor or its live-in
// list, this will catch a live-through case where the predecessor does not
// have the register in its live-in list. This currently only checks
// registers that have no aliases, are not allocatable and are not
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/MachineVerifier/test_g_build_vector.mir
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Expand Up @@ -16,17 +16,17 @@ body: |
; CHECK: Bad machine code: G_BUILD_VECTOR must produce a vector from scalar operands
%3:_(<2 x s32>) = G_BUILD_VECTOR %2

; CHECK: Bad machine code: G_BUILD_VECTOR must have an operand for each elemement
; CHECK: Bad machine code: G_BUILD_VECTOR must have an operand for each element
%4:_(<2 x s32>) = G_BUILD_VECTOR %0, %0, %0, %0

; CHECK: Bad machine code: G_BUILD_VECTOR result element type must match source type
; CHECK: Bad machine code: G_BUILD_VECTOR must have an operand for each elemement
; CHECK: Bad machine code: G_BUILD_VECTOR must have an operand for each element
%5:_(<4 x s16>) = G_BUILD_VECTOR %0, %0

%6:_(s16) = IMPLICIT_DEF

; CHECK: Bad machine code: G_BUILD_VECTOR result element type must match source type
; CHECK: Bad machine code: G_BUILD_VECTOR must have an operand for each elemement
; CHECK: Bad machine code: G_BUILD_VECTOR must have an operand for each element
%7:_(<2 x s32>) = G_BUILD_VECTOR %6, %6, %6, %6

%8:_(p0) = IMPLICIT_DEF
Expand Down