[X86][APX] Promote 8/16-bit LEA to 32-bit to avoid partial dependence #161051
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@llvm/pr-subscribers-backend-x86 Author: Phoebe Wang (phoebewang) ChangesFull diff: https://github.com/llvm/llvm-project/pull/161051.diff 4 Files Affected:
diff --git a/llvm/lib/Target/X86/X86InstrArithmetic.td b/llvm/lib/Target/X86/X86InstrArithmetic.td
index b476859069a57..031fdc1e7162c 100644
--- a/llvm/lib/Target/X86/X86InstrArithmetic.td
+++ b/llvm/lib/Target/X86/X86InstrArithmetic.td
@@ -25,18 +25,12 @@ let SchedRW = [WriteLEA] in {
[(set GR32:$dst, lea32addr:$src)]>,
OpSize32, Requires<[Not64BitMode]>;
- let Predicates = [HasNDD], isCodeGenOnly = 1 in {
- def LEA64_8r : I<0x8D, MRMSrcMem, (outs GR8:$dst), (ins lea64_8mem:$src),
- "lea{b}\t{$src|$dst}, {$dst|$src}",
- [(set GR8:$dst, lea64_iaddr:$src)]>,
- OpSize16,
- Requires<[In64BitMode]>;
-
- def LEA64_16r : I<0x8D, MRMSrcMem, (outs GR16:$dst), (ins lea64_16mem:$src),
- "lea{w}\t{$src|$dst}, {$dst|$src}",
- [(set GR16:$dst, lea64_iaddr:$src)]>,
- OpSize16,
- Requires<[In64BitMode]>;
+ let isCodeGenOnly = 1 in {
+ def LEA64_8r : I<0x8D, MRMSrcMem, (outs GR32:$dst), (ins lea64_8mem:$src),
+ "lea{l}\t{$src|$dst}, {$dst|$src}", []>, OpSize32;
+
+ def LEA64_16r : I<0x8D, MRMSrcMem, (outs GR32:$dst), (ins lea64_16mem:$src),
+ "lea{l}\t{$src|$dst}, {$dst|$src}", []>, OpSize32;
}
def LEA64_32r : I<0x8D, MRMSrcMem, (outs GR32:$dst), (ins lea64_32mem:$src),
@@ -51,6 +45,11 @@ let SchedRW = [WriteLEA] in {
[(set GR64:$dst, lea64addr:$src)]>;
} // SchedRW
+let Predicates = [HasNDD] in {
+ def : Pat<(i8 lea64_iaddr:$src), (EXTRACT_SUBREG (LEA64_8r lea64_8mem:$src), sub_8bit)>;
+ def : Pat<(i16 lea64_iaddr:$src), (EXTRACT_SUBREG (LEA64_16r lea64_16mem:$src), sub_16bit)>;
+}
+
// Pseudo instruction for lea that prevent optimizer from eliminating
// the instruction.
let SchedRW = [WriteLEA], isPseudo = true, hasSideEffects = 1 in {
diff --git a/llvm/test/CodeGen/X86/apx/ndd-neg-addr-index.ll b/llvm/test/CodeGen/X86/apx/ndd-neg-addr-index.ll
index 6679b5f58e8c1..41fa34667af86 100644
--- a/llvm/test/CodeGen/X86/apx/ndd-neg-addr-index.ll
+++ b/llvm/test/CodeGen/X86/apx/ndd-neg-addr-index.ll
@@ -8,7 +8,7 @@ define void @neg_8bit_1(i1 %cmp) {
; NDD-NEXT: andb $1, %dil, %al # encoding: [0x62,0xf4,0x7c,0x18,0x80,0xe7,0x01]
; NDD-NEXT: movzbl 0, %ecx # encoding: [0x0f,0xb6,0x0c,0x25,0x00,0x00,0x00,0x00]
; NDD-NEXT: negb %al, %al # encoding: [0x62,0xf4,0x7c,0x18,0xf6,0xd8]
-; NDD-NEXT: leab 2(%rcx,%rax), %al # encoding: [0x66,0x8d,0x44,0x01,0x02]
+; NDD-NEXT: leal 2(%rcx,%rax), %eax # encoding: [0x8d,0x44,0x01,0x02]
; NDD-NEXT: movb %al, 0 # encoding: [0x88,0x04,0x25,0x00,0x00,0x00,0x00]
; NDD-NEXT: retq # encoding: [0xc3]
entry:
@@ -25,7 +25,8 @@ define void @neg_8bit_2(i8 %int8) {
; NDD-NEXT: # kill: def $edi killed $edi def $rdi
; NDD-NEXT: addb %dil, %dil, %al # encoding: [0x62,0xf4,0x7c,0x18,0x00,0xff]
; NDD-NEXT: negb %al, %al # encoding: [0x62,0xf4,0x7c,0x18,0xf6,0xd8]
-; NDD-NEXT: leab 1(%rdi,%rax), %al # encoding: [0x66,0x8d,0x44,0x07,0x01]
+; NDD-NEXT: leal 1(%rdi,%rax), %eax # encoding: [0x8d,0x44,0x07,0x01]
+; NDD-NEXT: # kill: def $al killed $al killed $eax
; NDD-NEXT: mulb %dil # encoding: [0x40,0xf6,0xe7]
; NDD-NEXT: testb %al, %al # encoding: [0x84,0xc0]
; NDD-NEXT: retq # encoding: [0xc3]
@@ -55,7 +56,7 @@ define i32 @neg_16bit(i16 %0) {
; NDD-NEXT: cmovsl %ecx, %eax # EVEX TO LEGACY Compression encoding: [0x0f,0x48,0xc1]
; NDD-NEXT: andw $-256, %ax # EVEX TO LEGACY Compression encoding: [0x66,0x25,0x00,0xff]
; NDD-NEXT: negw %ax, %ax # encoding: [0x62,0xf4,0x7d,0x18,0xf7,0xd8]
-; NDD-NEXT: leaw 1(%rdi,%rax), %ax # encoding: [0x66,0x8d,0x44,0x07,0x01]
+; NDD-NEXT: leal 1(%rdi,%rax), %eax # encoding: [0x8d,0x44,0x07,0x01]
; NDD-NEXT: movzwl %ax, %eax # encoding: [0x0f,0xb7,0xc0]
; NDD-NEXT: movq %rax, 0 # encoding: [0x48,0x89,0x04,0x25,0x00,0x00,0x00,0x00]
; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
diff --git a/llvm/test/CodeGen/X86/lea-16bit.ll b/llvm/test/CodeGen/X86/lea-16bit.ll
index cec29ab1da6ab..40da01d9ab8f3 100644
--- a/llvm/test/CodeGen/X86/lea-16bit.ll
+++ b/llvm/test/CodeGen/X86/lea-16bit.ll
@@ -13,7 +13,8 @@ define i16 @lea16bit(i16 %in) {
; NDD-LABEL: lea16bit:
; NDD: # %bb.0:
; NDD-NEXT: # kill: def $edi killed $edi def $rdi
-; NDD-NEXT: leaw 1(%rdi,%rdi), %ax
+; NDD-NEXT: leal 1(%rdi,%rdi), %eax
+; NDD-NEXT: # kill: def $ax killed $ax killed $eax
; NDD-NEXT: retq
%shl = shl i16 %in, 1
%or = or i16 %shl, 1
diff --git a/llvm/test/CodeGen/X86/lea-8bit.ll b/llvm/test/CodeGen/X86/lea-8bit.ll
index 98222dfc0407c..fc295f75e23c7 100644
--- a/llvm/test/CodeGen/X86/lea-8bit.ll
+++ b/llvm/test/CodeGen/X86/lea-8bit.ll
@@ -14,7 +14,8 @@ define i8 @lea8bit(i8 %in) {
; NDD-LABEL: lea8bit:
; NDD: # %bb.0:
; NDD-NEXT: # kill: def $edi killed $edi def $rdi
-; NDD-NEXT: leab 1(%rdi,%rdi), %al
+; NDD-NEXT: leal 1(%rdi,%rdi), %eax
+; NDD-NEXT: # kill: def $al killed $al killed $eax
; NDD-NEXT: retq
%shl = shl i8 %in, 1
%or = or i8 %shl, 1
|
Yes, it's only used by MC for disassembling. Here we just use the nodes during codegen. |
@KanRobert do we use it here to block generating APX instructions when using |
I don't think so, and I don't understand why we need the predicate HasNDD here, it was added by |
|
Why is this APX-specific? It seems applicable for 64-bit. |
Thanks to 20683de, only when NDD enabled the 8/16-bit LEA can be selected. |
KanRobert
approved these changes
Sep 29, 2025
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/116/builds/19009 Here is the relevant piece of the build log for the reference |
mahesh-attarde
pushed a commit
to mahesh-attarde/llvm-project
that referenced
this pull request
Oct 3, 2025
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