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Oct 31, 2025
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[LoongArch] Add patterns to support vector type average instructions generation #161079

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62fbbf5
[LoongArch] Add patterns to support vector type average instructions …
zhaoqi5 Sep 28, 2025
2b79992
update tests
zhaoqi5 Sep 28, 2025
f644f90
using multiclass
zhaoqi5 Sep 29, 2025
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18 changes: 18 additions & 0 deletions llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -2024,6 +2024,24 @@ def : Pat<(v4i32(fp_to_uint v4f64:$vj)),
(XVFTINTRZ_LU_D v4f64:$vj)),
sub_128)>;

// XVAVG_{B/H/W/D/BU/HU/WU/DU}, XVAVGR_{B/H/W/D/BU/HU/WU/DU}
defm : VAvgPat<sra, "XVAVG_B", v32i8>;
defm : VAvgPat<sra, "XVAVG_H", v16i16>;
defm : VAvgPat<sra, "XVAVG_W", v8i32>;
defm : VAvgPat<sra, "XVAVG_D", v4i64>;
defm : VAvgPat<srl, "XVAVG_BU", v32i8>;
defm : VAvgPat<srl, "XVAVG_HU", v16i16>;
defm : VAvgPat<srl, "XVAVG_WU", v8i32>;
defm : VAvgPat<srl, "XVAVG_DU", v4i64>;
defm : VAvgrPat<sra, "XVAVGR_B", v32i8>;
defm : VAvgrPat<sra, "XVAVGR_H", v16i16>;
defm : VAvgrPat<sra, "XVAVGR_W", v8i32>;
defm : VAvgrPat<sra, "XVAVGR_D", v4i64>;
defm : VAvgrPat<srl, "XVAVGR_BU", v32i8>;
defm : VAvgrPat<srl, "XVAVGR_HU", v16i16>;
defm : VAvgrPat<srl, "XVAVGR_WU", v8i32>;
defm : VAvgrPat<srl, "XVAVGR_DU", v4i64>;

// abs
def : Pat<(abs v32i8:$xj), (XVSIGNCOV_B v32i8:$xj, v32i8:$xj)>;
def : Pat<(abs v16i16:$xj), (XVSIGNCOV_H v16i16:$xj, v16i16:$xj)>;
Expand Down
30 changes: 30 additions & 0 deletions llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
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Expand Up @@ -1518,6 +1518,18 @@ multiclass InsertExtractPatV2<ValueType vecty, ValueType elemty> {
}
}

multiclass VAvgPat<SDPatternOperator OpNode, string Inst, ValueType vt> {
def : Pat<(OpNode (vt (add vt:$vj, vt:$vk)), (vt (vsplat_imm_eq_1))),
(!cast<LAInst>(Inst) vt:$vj, vt:$vk)>;
}

multiclass VAvgrPat<SDPatternOperator OpNode, string Inst, ValueType vt> {
def : Pat<(OpNode (vt (add (vt (add vt:$vj, vt:$vk)),
(vt (vsplat_imm_eq_1)))),
(vt (vsplat_imm_eq_1))),
(!cast<LAInst>(Inst) vt:$vj, vt:$vk)>;
}

let Predicates = [HasExtLSX] in {

// VADD_{B/H/W/D}
Expand Down Expand Up @@ -2154,6 +2166,24 @@ def : Pat<(f32 f32imm_vldi:$in),
def : Pat<(f64 f64imm_vldi:$in),
(f64 (EXTRACT_SUBREG (VLDI (to_f64imm_vldi f64imm_vldi:$in)), sub_64))>;

// VAVG_{B/H/W/D/BU/HU/WU/DU}, VAVGR_{B/H/W/D/BU/HU/WU/DU}
defm : VAvgPat<sra, "VAVG_B", v16i8>;
defm : VAvgPat<sra, "VAVG_H", v8i16>;
defm : VAvgPat<sra, "VAVG_W", v4i32>;
defm : VAvgPat<sra, "VAVG_D", v2i64>;
defm : VAvgPat<srl, "VAVG_BU", v16i8>;
defm : VAvgPat<srl, "VAVG_HU", v8i16>;
defm : VAvgPat<srl, "VAVG_WU", v4i32>;
defm : VAvgPat<srl, "VAVG_DU", v2i64>;
defm : VAvgrPat<sra, "VAVGR_B", v16i8>;
defm : VAvgrPat<sra, "VAVGR_H", v8i16>;
defm : VAvgrPat<sra, "VAVGR_W", v4i32>;
defm : VAvgrPat<sra, "VAVGR_D", v2i64>;
defm : VAvgrPat<srl, "VAVGR_BU", v16i8>;
defm : VAvgrPat<srl, "VAVGR_HU", v8i16>;
defm : VAvgrPat<srl, "VAVGR_WU", v4i32>;
defm : VAvgrPat<srl, "VAVGR_DU", v2i64>;

// abs
def : Pat<(abs v16i8:$vj), (VSIGNCOV_B v16i8:$vj, v16i8:$vj)>;
def : Pat<(abs v8i16:$vj), (VSIGNCOV_H v8i16:$vj, v8i16:$vj)>;
Expand Down
146 changes: 80 additions & 66 deletions llvm/test/CodeGen/LoongArch/lasx/ir-instruction/avg.ll
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@@ -1,14 +1,13 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64

define void @xvavg_b(ptr %res, ptr %a, ptr %b) nounwind {
; CHECK-LABEL: xvavg_b:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvld $xr0, $a1, 0
; CHECK-NEXT: xvld $xr1, $a2, 0
; CHECK-NEXT: xvadd.b $xr0, $xr0, $xr1
; CHECK-NEXT: xvsrai.b $xr0, $xr0, 1
; CHECK-NEXT: xvavg.b $xr0, $xr0, $xr1
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
Expand All @@ -25,8 +24,7 @@ define void @xvavg_h(ptr %res, ptr %a, ptr %b) nounwind {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvld $xr0, $a1, 0
; CHECK-NEXT: xvld $xr1, $a2, 0
; CHECK-NEXT: xvadd.h $xr0, $xr0, $xr1
; CHECK-NEXT: xvsrai.h $xr0, $xr0, 1
; CHECK-NEXT: xvavg.h $xr0, $xr0, $xr1
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
Expand All @@ -43,8 +41,7 @@ define void @xvavg_w(ptr %res, ptr %a, ptr %b) nounwind {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvld $xr0, $a1, 0
; CHECK-NEXT: xvld $xr1, $a2, 0
; CHECK-NEXT: xvadd.w $xr0, $xr0, $xr1
; CHECK-NEXT: xvsrai.w $xr0, $xr0, 1
; CHECK-NEXT: xvavg.w $xr0, $xr0, $xr1
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
Expand All @@ -57,14 +54,22 @@ entry:
}

define void @xvavg_d(ptr %res, ptr %a, ptr %b) nounwind {
; CHECK-LABEL: xvavg_d:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvld $xr0, $a1, 0
; CHECK-NEXT: xvld $xr1, $a2, 0
; CHECK-NEXT: xvadd.d $xr0, $xr0, $xr1
; CHECK-NEXT: xvsrai.d $xr0, $xr0, 1
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
; LA32-LABEL: xvavg_d:
; LA32: # %bb.0: # %entry
; LA32-NEXT: xvld $xr0, $a1, 0
; LA32-NEXT: xvld $xr1, $a2, 0
; LA32-NEXT: xvadd.d $xr0, $xr0, $xr1
; LA32-NEXT: xvsrai.d $xr0, $xr0, 1
; LA32-NEXT: xvst $xr0, $a0, 0
; LA32-NEXT: ret
;
; LA64-LABEL: xvavg_d:
; LA64: # %bb.0: # %entry
; LA64-NEXT: xvld $xr0, $a1, 0
; LA64-NEXT: xvld $xr1, $a2, 0
; LA64-NEXT: xvavg.d $xr0, $xr0, $xr1
; LA64-NEXT: xvst $xr0, $a0, 0
; LA64-NEXT: ret
entry:
%va = load <4 x i64>, ptr %a
%vb = load <4 x i64>, ptr %b
Expand All @@ -79,8 +84,7 @@ define void @xvavg_bu(ptr %res, ptr %a, ptr %b) nounwind {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvld $xr0, $a1, 0
; CHECK-NEXT: xvld $xr1, $a2, 0
; CHECK-NEXT: xvadd.b $xr0, $xr0, $xr1
; CHECK-NEXT: xvsrli.b $xr0, $xr0, 1
; CHECK-NEXT: xvavg.bu $xr0, $xr0, $xr1
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
Expand All @@ -97,8 +101,7 @@ define void @xvavg_hu(ptr %res, ptr %a, ptr %b) nounwind {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvld $xr0, $a1, 0
; CHECK-NEXT: xvld $xr1, $a2, 0
; CHECK-NEXT: xvadd.h $xr0, $xr0, $xr1
; CHECK-NEXT: xvsrli.h $xr0, $xr0, 1
; CHECK-NEXT: xvavg.hu $xr0, $xr0, $xr1
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
Expand All @@ -115,8 +118,7 @@ define void @xvavg_wu(ptr %res, ptr %a, ptr %b) nounwind {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvld $xr0, $a1, 0
; CHECK-NEXT: xvld $xr1, $a2, 0
; CHECK-NEXT: xvadd.w $xr0, $xr0, $xr1
; CHECK-NEXT: xvsrli.w $xr0, $xr0, 1
; CHECK-NEXT: xvavg.wu $xr0, $xr0, $xr1
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
Expand All @@ -129,14 +131,22 @@ entry:
}

define void @xvavg_du(ptr %res, ptr %a, ptr %b) nounwind {
; CHECK-LABEL: xvavg_du:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvld $xr0, $a1, 0
; CHECK-NEXT: xvld $xr1, $a2, 0
; CHECK-NEXT: xvadd.d $xr0, $xr0, $xr1
; CHECK-NEXT: xvsrli.d $xr0, $xr0, 1
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
; LA32-LABEL: xvavg_du:
; LA32: # %bb.0: # %entry
; LA32-NEXT: xvld $xr0, $a1, 0
; LA32-NEXT: xvld $xr1, $a2, 0
; LA32-NEXT: xvadd.d $xr0, $xr0, $xr1
; LA32-NEXT: xvsrli.d $xr0, $xr0, 1
; LA32-NEXT: xvst $xr0, $a0, 0
; LA32-NEXT: ret
;
; LA64-LABEL: xvavg_du:
; LA64: # %bb.0: # %entry
; LA64-NEXT: xvld $xr0, $a1, 0
; LA64-NEXT: xvld $xr1, $a2, 0
; LA64-NEXT: xvavg.du $xr0, $xr0, $xr1
; LA64-NEXT: xvst $xr0, $a0, 0
; LA64-NEXT: ret
entry:
%va = load <4 x i64>, ptr %a
%vb = load <4 x i64>, ptr %b
Expand All @@ -151,9 +161,7 @@ define void @xvavgr_b(ptr %res, ptr %a, ptr %b) nounwind {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvld $xr0, $a1, 0
; CHECK-NEXT: xvld $xr1, $a2, 0
; CHECK-NEXT: xvadd.b $xr0, $xr0, $xr1
; CHECK-NEXT: xvaddi.bu $xr0, $xr0, 1
; CHECK-NEXT: xvsrai.b $xr0, $xr0, 1
; CHECK-NEXT: xvavgr.b $xr0, $xr0, $xr1
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
Expand All @@ -171,9 +179,7 @@ define void @xvavgr_h(ptr %res, ptr %a, ptr %b) nounwind {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvld $xr0, $a1, 0
; CHECK-NEXT: xvld $xr1, $a2, 0
; CHECK-NEXT: xvadd.h $xr0, $xr0, $xr1
; CHECK-NEXT: xvaddi.hu $xr0, $xr0, 1
; CHECK-NEXT: xvsrai.h $xr0, $xr0, 1
; CHECK-NEXT: xvavgr.h $xr0, $xr0, $xr1
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
Expand All @@ -191,9 +197,7 @@ define void @xvavgr_w(ptr %res, ptr %a, ptr %b) nounwind {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvld $xr0, $a1, 0
; CHECK-NEXT: xvld $xr1, $a2, 0
; CHECK-NEXT: xvadd.w $xr0, $xr0, $xr1
; CHECK-NEXT: xvaddi.wu $xr0, $xr0, 1
; CHECK-NEXT: xvsrai.w $xr0, $xr0, 1
; CHECK-NEXT: xvavgr.w $xr0, $xr0, $xr1
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
Expand All @@ -207,15 +211,23 @@ entry:
}

define void @xvavgr_d(ptr %res, ptr %a, ptr %b) nounwind {
; CHECK-LABEL: xvavgr_d:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvld $xr0, $a1, 0
; CHECK-NEXT: xvld $xr1, $a2, 0
; CHECK-NEXT: xvadd.d $xr0, $xr0, $xr1
; CHECK-NEXT: xvaddi.du $xr0, $xr0, 1
; CHECK-NEXT: xvsrai.d $xr0, $xr0, 1
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
; LA32-LABEL: xvavgr_d:
; LA32: # %bb.0: # %entry
; LA32-NEXT: xvld $xr0, $a1, 0
; LA32-NEXT: xvld $xr1, $a2, 0
; LA32-NEXT: xvadd.d $xr0, $xr0, $xr1
; LA32-NEXT: xvaddi.du $xr0, $xr0, 1
; LA32-NEXT: xvsrai.d $xr0, $xr0, 1
; LA32-NEXT: xvst $xr0, $a0, 0
; LA32-NEXT: ret
;
; LA64-LABEL: xvavgr_d:
; LA64: # %bb.0: # %entry
; LA64-NEXT: xvld $xr0, $a1, 0
; LA64-NEXT: xvld $xr1, $a2, 0
; LA64-NEXT: xvavgr.d $xr0, $xr0, $xr1
; LA64-NEXT: xvst $xr0, $a0, 0
; LA64-NEXT: ret
entry:
%va = load <4 x i64>, ptr %a
%vb = load <4 x i64>, ptr %b
Expand All @@ -231,9 +243,7 @@ define void @xvavgr_bu(ptr %res, ptr %a, ptr %b) nounwind {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvld $xr0, $a1, 0
; CHECK-NEXT: xvld $xr1, $a2, 0
; CHECK-NEXT: xvadd.b $xr0, $xr0, $xr1
; CHECK-NEXT: xvaddi.bu $xr0, $xr0, 1
; CHECK-NEXT: xvsrli.b $xr0, $xr0, 1
; CHECK-NEXT: xvavgr.bu $xr0, $xr0, $xr1
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
Expand All @@ -251,9 +261,7 @@ define void @xvavgr_hu(ptr %res, ptr %a, ptr %b) nounwind {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvld $xr0, $a1, 0
; CHECK-NEXT: xvld $xr1, $a2, 0
; CHECK-NEXT: xvadd.h $xr0, $xr0, $xr1
; CHECK-NEXT: xvaddi.hu $xr0, $xr0, 1
; CHECK-NEXT: xvsrli.h $xr0, $xr0, 1
; CHECK-NEXT: xvavgr.hu $xr0, $xr0, $xr1
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
Expand All @@ -271,9 +279,7 @@ define void @xvavgr_wu(ptr %res, ptr %a, ptr %b) nounwind {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvld $xr0, $a1, 0
; CHECK-NEXT: xvld $xr1, $a2, 0
; CHECK-NEXT: xvadd.w $xr0, $xr0, $xr1
; CHECK-NEXT: xvaddi.wu $xr0, $xr0, 1
; CHECK-NEXT: xvsrli.w $xr0, $xr0, 1
; CHECK-NEXT: xvavgr.wu $xr0, $xr0, $xr1
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
Expand All @@ -287,15 +293,23 @@ entry:
}

define void @xvavgr_du(ptr %res, ptr %a, ptr %b) nounwind {
; CHECK-LABEL: xvavgr_du:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvld $xr0, $a1, 0
; CHECK-NEXT: xvld $xr1, $a2, 0
; CHECK-NEXT: xvadd.d $xr0, $xr0, $xr1
; CHECK-NEXT: xvaddi.du $xr0, $xr0, 1
; CHECK-NEXT: xvsrli.d $xr0, $xr0, 1
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
; LA32-LABEL: xvavgr_du:
; LA32: # %bb.0: # %entry
; LA32-NEXT: xvld $xr0, $a1, 0
; LA32-NEXT: xvld $xr1, $a2, 0
; LA32-NEXT: xvadd.d $xr0, $xr0, $xr1
; LA32-NEXT: xvaddi.du $xr0, $xr0, 1
; LA32-NEXT: xvsrli.d $xr0, $xr0, 1
; LA32-NEXT: xvst $xr0, $a0, 0
; LA32-NEXT: ret
;
; LA64-LABEL: xvavgr_du:
; LA64: # %bb.0: # %entry
; LA64-NEXT: xvld $xr0, $a1, 0
; LA64-NEXT: xvld $xr1, $a2, 0
; LA64-NEXT: xvavgr.du $xr0, $xr0, $xr1
; LA64-NEXT: xvst $xr0, $a0, 0
; LA64-NEXT: ret
entry:
%va = load <4 x i64>, ptr %a
%vb = load <4 x i64>, ptr %b
Expand Down
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