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fix isCall flag for JAL and JALR, and the isBranch flag for C_JR #161105

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fix isCall flag for JAL and JALR, and the isBranch flag for C_JR #161105

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14 changes: 8 additions & 6 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -752,13 +752,15 @@ def LUI : RVInstU<OPC_LUI, (outs GPR:$rd), (ins uimm20_lui:$imm20),
def AUIPC : RVInstU<OPC_AUIPC, (outs GPR:$rd), (ins uimm20_auipc:$imm20),
"auipc", "$rd, $imm20">, Sched<[WriteIALU]>;

def JAL : RVInstJ<OPC_JAL, (outs GPR:$rd), (ins simm21_lsb0_jal:$imm20),
"jal", "$rd, $imm20">, Sched<[WriteJal]>;
let isCall = 1 in {
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Both of these instructions are not a call if the destination is X0. The RET pseudoinstruciton for example is JALR with rd=x0 and rs1=x0.

def JAL : RVInstJ<OPC_JAL, (outs GPR:$rd), (ins simm21_lsb0_jal:$imm20),
"jal", "$rd, $imm20">, Sched<[WriteJal]>;

def JALR : RVInstI<0b000, OPC_JALR, (outs GPR:$rd),
(ins GPR:$rs1, simm12_lo:$imm12),
"jalr", "$rd, ${imm12}(${rs1})">,
Sched<[WriteJalr, ReadJalr]>;
def JALR : RVInstI<0b000, OPC_JALR, (outs GPR:$rd),
(ins GPR:$rs1, simm12_lo:$imm12),
"jalr", "$rd, ${imm12}(${rs1})">,
Sched<[WriteJalr, ReadJalr]>;
}
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0

def BEQ : BranchCC_rri<0b000, "beq">;
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1 change: 1 addition & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfoC.td
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Expand Up @@ -488,6 +488,7 @@ def C_LDSP : CStackLoad<0b011, "c.ldsp", GPRNoX0, uimm9_lsb000>,
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
def C_JR : RVInst16CR<0b1000, 0b10, (outs), (ins GPRNoX0:$rs1),
"c.jr", "$rs1">, Sched<[WriteJalr, ReadJalr]> {
let isBranch = 1;
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c.jr is not a branch if rs1=x1. It's a return.

let isBarrier = 1;
let isTerminator = 1;
let rs2 = 0;
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