[LV] Increase coverage of uniformity-rewriter

[artagnon]

Add a test with a non-uniform load of an argument (SCEVUnknown), showing that SCEVUnknown cannot always be considered uniform.

[llvmbot]

@llvm/pr-subscribers-llvm-transforms

Author: Ramkumar Ramachandra (artagnon)

Changes

Add a test with a maybe-uniform load of an argument (SCEVUnknown), showing that SCEVAddRecForUniformityRewriter bails out when it sees that the top-level select expression doesn't contain a UDivExpr.

---

Full diff: https://github.com/llvm/llvm-project/pull/161219.diff

1 Files Affected:

• (added) llvm/test/Transforms/LoopVectorize/uniformity-rewriter.ll (+76)

diff --git a/llvm/test/Transforms/LoopVectorize/uniformity-rewriter.ll b/llvm/test/Transforms/LoopVectorize/uniformity-rewriter.ll
new file mode 100644
index 0000000000000..8f65b07c0797a
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/uniformity-rewriter.ll
@@ -0,0 +1,76 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6
+; RUN: opt -passes=loop-vectorize -force-vector-width=4 -S %s | FileCheck %s
+
+; Test to exercise the uniformity rewriter.
+
+define i32 @uniformityrew(ptr %src, i32 %x, i1 %c, i64 %n) {
+; CHECK-LABEL: define i32 @uniformityrew(
+; CHECK-SAME: ptr [[SRC:%.*]], i32 [[X:%.*]], i1 [[C:%.*]], i64 [[N:%.*]]) {
+; CHECK-NEXT:  [[ENTRY:.*]]:
+; CHECK-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4
+; CHECK-NEXT:    br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK:       [[VECTOR_PH]]:
+; CHECK-NEXT:    [[N_MOD_VF:%.*]] = urem i64 [[N]], 4
+; CHECK-NEXT:    [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
+; CHECK-NEXT:    [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[X]], i64 0
+; CHECK-NEXT:    [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP0:%.*]] = ashr <4 x i32> [[BROADCAST_SPLAT]], splat (i32 1)
+; CHECK-NEXT:    [[TMP6:%.*]] = and <4 x i32> [[TMP0]], splat (i32 1)
+; CHECK-NEXT:    [[TMP7:%.*]] = xor <4 x i32> [[TMP6]], splat (i32 1)
+; CHECK-NEXT:    [[TMP8:%.*]] = zext <4 x i32> [[TMP7]] to <4 x i64>
+; CHECK-NEXT:    [[TMP9:%.*]] = getelementptr i32, ptr [[SRC]], <4 x i64> [[TMP8]]
+; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]
+; CHECK:       [[VECTOR_BODY]]:
+; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT:    [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT:    [[TMP10:%.*]] = getelementptr i32, ptr [[SRC]], <4 x i64> [[VEC_IND]]
+; CHECK-NEXT:    [[TMP11:%.*]] = select i1 [[C]], <4 x ptr> [[TMP9]], <4 x ptr> [[TMP10]]
+; CHECK-NEXT:    [[TMP12:%.*]] = extractelement <4 x ptr> [[TMP11]], i32 3
+; CHECK-NEXT:    [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4
+; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
+; CHECK-NEXT:    [[VEC_IND_NEXT]] = add <4 x i64> [[VEC_IND]], splat (i64 4)
+; CHECK-NEXT:    [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT:    br i1 [[TMP14]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK:       [[MIDDLE_BLOCK]]:
+; CHECK-NEXT:    [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
+; CHECK-NEXT:    br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK:       [[SCALAR_PH]]:
+; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT:    br label %[[LOOP:.*]]
+; CHECK:       [[LOOP]]:
+; CHECK-NEXT:    [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT:    [[ASHR_X:%.*]] = ashr i32 [[X]], 1
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[ASHR_X]], 1
+; CHECK-NEXT:    [[XOR:%.*]] = xor i32 [[AND]], 1
+; CHECK-NEXT:    [[IDX_EXT_1:%.*]] = zext i32 [[XOR]] to i64
+; CHECK-NEXT:    [[GEP_INVARIANT:%.*]] = getelementptr i32, ptr [[SRC]], i64 [[IDX_EXT_1]]
+; CHECK-NEXT:    [[GEP_IV:%.*]] = getelementptr i32, ptr [[SRC]], i64 [[IV]]
+; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[C]], ptr [[GEP_INVARIANT]], ptr [[GEP_IV]]
+; CHECK-NEXT:    [[LD_SRC:%.*]] = load i32, ptr [[SEL]], align 4
+; CHECK-NEXT:    [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-NEXT:    [[EXIT_COND:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
+; CHECK-NEXT:    br i1 [[EXIT_COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK:       [[EXIT]]:
+; CHECK-NEXT:    [[LD_SRC_LCSSA:%.*]] = phi i32 [ [[LD_SRC]], %[[LOOP]] ], [ [[TMP13]], %[[MIDDLE_BLOCK]] ]
+; CHECK-NEXT:    ret i32 [[LD_SRC_LCSSA]]
+;
+entry:
+  br label %loop
+
+loop:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+  %ashr.x = ashr i32 %x, 1
+  %and = and i32 %ashr.x, 1
+  %xor = xor i32 %and, 1
+  %idx.ext.1 = zext i32 %xor to i64
+  %gep.invariant = getelementptr i32, ptr %src, i64 %idx.ext.1
+  %gep.iv = getelementptr i32, ptr %src, i64 %iv
+  %sel = select i1 %c, ptr %gep.invariant, ptr %gep.iv
+  %ld.src = load i32, ptr %sel, align 4
+  %iv.next = add i64 %iv, 1
+  %exit.cond = icmp eq i64 %iv.next, %n
+  br i1 %exit.cond, label %exit, label %loop
+
+exit:
+  ret i32 %ld.src
+}

[artagnon]

Gentle ping.

[fhahn]

Thanks for adding the test. Could this be added to one if the existing uniform with div/Lahr tests as negative coverage?

[artagnon]

Gentle ping.

[fhahn]

LGTM, thanks