Skip to content

[LoongArch] Custom legalize vselect to vector_shuffle for most constant condition cases #163489

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 2 commits into
base: main
Choose a base branch
from
+142 −72
Open

[LoongArch] Custom legalize vselect to vector_shuffle for most constant condition cases #163489

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
31e5b93
[LoongArch] Custom legalize vselect to vector_shuffle for most consta…
zhaoqi5 Oct 15, 2025
636d1de
fix typo
zhaoqi5 Nov 21, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
51 changes: 49 additions & 2 deletions llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -327,7 +327,7 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::BUILD_VECTOR, VT, Custom);

setOperationAction(ISD::SETCC, VT, Legal);
setOperationAction(ISD::VSELECT, VT, Legal);
setOperationAction(ISD::VSELECT, VT, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
}
Expand Down Expand Up @@ -415,7 +415,7 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::INSERT_SUBVECTOR, VT, Legal);

setOperationAction(ISD::SETCC, VT, Legal);
setOperationAction(ISD::VSELECT, VT, Legal);
setOperationAction(ISD::VSELECT, VT, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
}
for (MVT VT : {MVT::v4i64, MVT::v8i32, MVT::v16i16, MVT::v32i8}) {
Expand Down Expand Up @@ -611,10 +611,57 @@ SDValue LoongArchTargetLowering::LowerOperation(SDValue Op,
return lowerVECREDUCE(Op, DAG);
case ISD::ConstantFP:
return lowerConstantFP(Op, DAG);
case ISD::VSELECT:
return lowerVSELECT(Op, DAG);
}
return SDValue();
}

SDValue LoongArchTargetLowering::lowerVSELECT(SDValue Op,
SelectionDAG &DAG) const {
SDValue Cond = Op.getOperand(0);
SDValue LHS = Op.getOperand(1);
SDValue RHS = Op.getOperand(2);
MVT VT = Op.getSimpleValueType();
SDLoc DL(Op);

// Try to lower vselect to vector_shuffle. All cases with constant
// build_vector condition will be handled. NOTE: On 32-bit platform, vselect
// with v2i64/v4i64 type condition will never enter this because of the extra
// bitcast. It can be considered separately later.
if (ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Cond.getNode());
APInt SplatValue, SplatUndef;
unsigned SplatBitSize;
bool HasAnyUndefs;

// If the Cond is a BUILD_VECTOR with splat constants, using a vldi or
// constant broadcast instruction and a vbitsel is better.
if (BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
/*MinSplatBits=*/8) &&
(SplatBitSize == 8 || SplatBitSize == 16 || SplatBitSize == 32 ||
SplatBitSize == 64))
return Op;

SmallVector<int, 32> Mask;
EVT CondVT = Cond.getValueType();
int NumElts = CondVT.getVectorNumElements();
Mask.resize(NumElts, -1);
for (int i = 0; i < NumElts; ++i) {
auto *CondElt = dyn_cast<ConstantSDNode>(Cond.getOperand(i));
if (CondElt->getZExtValue() == 0)
Mask[i] = i + NumElts;
else
Mask[i] = i;
}

return DAG.getVectorShuffle(VT, DL, LHS, RHS, Mask);
}

// Fallback to match patterns in tablegen.
return Op;
}

SDValue LoongArchTargetLowering::lowerConstantFP(SDValue Op,
SelectionDAG &DAG) const {
EVT VT = Op.getValueType();
Expand Down
1 change: 1 addition & 0 deletions llvm/lib/Target/LoongArch/LoongArchISelLowering.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -239,6 +239,7 @@ class LoongArchTargetLowering : public TargetLowering {
SDValue lowerVECREDUCE_ADD(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerConstantFP(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerVSELECT(SDValue Op, SelectionDAG &DAG) const;

bool isFPImmLegal(const APFloat &Imm, EVT VT,
bool ForCodeSize) const override;
Expand Down
84 changes: 48 additions & 36 deletions llvm/test/CodeGen/LoongArch/lasx/vselect.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64

define void @select_v32i8_imm(ptr %res, ptr %a0) nounwind {
; CHECK-LABEL: select_v32i8_imm:
Expand Down Expand Up @@ -37,10 +37,8 @@ define void @select_v32i8_1(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: xvld $xr0, $a1, 0
; CHECK-NEXT: xvld $xr1, $a2, 0
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI2_0)
; CHECK-NEXT: xvld $xr2, $a1, %pc_lo12(.LCPI2_0)
; CHECK-NEXT: xvbitsel.v $xr0, $xr1, $xr0, $xr2
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: xvinsve0.w $xr1, $xr0, 0
; CHECK-NEXT: xvst $xr1, $a0, 0
; CHECK-NEXT: ret
%v0 = load <32 x i8>, ptr %a0
%v1 = load <32 x i8>, ptr %a1
Expand All @@ -56,7 +54,7 @@ define void @select_v32i8_2(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK-NEXT: xvld $xr1, $a2, 0
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI3_0)
; CHECK-NEXT: xvld $xr2, $a1, %pc_lo12(.LCPI3_0)
; CHECK-NEXT: xvbitsel.v $xr0, $xr1, $xr0, $xr2
; CHECK-NEXT: xvshuf.b $xr0, $xr1, $xr0, $xr2
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
%v0 = load <32 x i8>, ptr %a0
Expand Down Expand Up @@ -88,9 +86,7 @@ define void @select_v16i16_1(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: xvld $xr0, $a1, 0
; CHECK-NEXT: xvld $xr1, $a2, 0
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI5_0)
; CHECK-NEXT: xvld $xr2, $a1, %pc_lo12(.LCPI5_0)
; CHECK-NEXT: xvbitsel.v $xr0, $xr1, $xr0, $xr2
; CHECK-NEXT: xvinsve0.w $xr0, $xr1, 0
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
%v0 = load <16 x i16>, ptr %a0
Expand All @@ -107,8 +103,8 @@ define void @select_v16i16_2(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK-NEXT: xvld $xr1, $a2, 0
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI6_0)
; CHECK-NEXT: xvld $xr2, $a1, %pc_lo12(.LCPI6_0)
; CHECK-NEXT: xvbitsel.v $xr0, $xr1, $xr0, $xr2
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: xvshuf.h $xr2, $xr1, $xr0
; CHECK-NEXT: xvst $xr2, $a0, 0
; CHECK-NEXT: ret
%v0 = load <16 x i16>, ptr %a0
%v1 = load <16 x i16>, ptr %a1
Expand Down Expand Up @@ -138,10 +134,8 @@ define void @select_v8i32_1(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: xvld $xr0, $a1, 0
; CHECK-NEXT: xvld $xr1, $a2, 0
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI8_0)
; CHECK-NEXT: xvld $xr2, $a1, %pc_lo12(.LCPI8_0)
; CHECK-NEXT: xvbitsel.v $xr0, $xr1, $xr0, $xr2
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: xvinsve0.d $xr1, $xr0, 0
; CHECK-NEXT: xvst $xr1, $a0, 0
; CHECK-NEXT: ret
%v0 = load <8 x i32>, ptr %a0
%v1 = load <8 x i32>, ptr %a1
Expand All @@ -157,8 +151,8 @@ define void @select_v8f32(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK-NEXT: xvld $xr1, $a2, 0
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI9_0)
; CHECK-NEXT: xvld $xr2, $a1, %pc_lo12(.LCPI9_0)
; CHECK-NEXT: xvbitsel.v $xr0, $xr1, $xr0, $xr2
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: xvshuf.w $xr2, $xr1, $xr0
; CHECK-NEXT: xvst $xr2, $a0, 0
; CHECK-NEXT: ret
%v0 = load <8 x float>, ptr %a0
%v1 = load <8 x float>, ptr %a1
Expand All @@ -168,15 +162,23 @@ define void @select_v8f32(ptr %res, ptr %a0, ptr %a1) nounwind {
}

define void @select_v4i64(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK-LABEL: select_v4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: xvld $xr0, $a1, 0
; CHECK-NEXT: xvld $xr1, $a2, 0
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI10_0)
; CHECK-NEXT: xvld $xr2, $a1, %pc_lo12(.LCPI10_0)
; CHECK-NEXT: xvbitsel.v $xr0, $xr1, $xr0, $xr2
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
; LA32-LABEL: select_v4i64:
; LA32: # %bb.0:
; LA32-NEXT: xvld $xr0, $a1, 0
; LA32-NEXT: xvld $xr1, $a2, 0
; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI10_0)
; LA32-NEXT: xvld $xr2, $a1, %pc_lo12(.LCPI10_0)
; LA32-NEXT: xvbitsel.v $xr0, $xr1, $xr0, $xr2
; LA32-NEXT: xvst $xr0, $a0, 0
; LA32-NEXT: ret
;
; LA64-LABEL: select_v4i64:
; LA64: # %bb.0:
; LA64-NEXT: xvld $xr0, $a1, 0
; LA64-NEXT: xvld $xr1, $a2, 0
; LA64-NEXT: xvinsve0.d $xr1, $xr0, 0
; LA64-NEXT: xvst $xr1, $a0, 0
; LA64-NEXT: ret
%v0 = load <4 x i64>, ptr %a0
%v1 = load <4 x i64>, ptr %a1
%sel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i64> %v0, <4 x i64> %v1
Expand All @@ -185,15 +187,25 @@ define void @select_v4i64(ptr %res, ptr %a0, ptr %a1) nounwind {
}

define void @select_v4f64(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK-LABEL: select_v4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: xvld $xr0, $a1, 0
; CHECK-NEXT: xvld $xr1, $a2, 0
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI11_0)
; CHECK-NEXT: xvld $xr2, $a1, %pc_lo12(.LCPI11_0)
; CHECK-NEXT: xvbitsel.v $xr0, $xr1, $xr0, $xr2
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
; LA32-LABEL: select_v4f64:
; LA32: # %bb.0:
; LA32-NEXT: xvld $xr0, $a1, 0
; LA32-NEXT: xvld $xr1, $a2, 0
; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI11_0)
; LA32-NEXT: xvld $xr2, $a1, %pc_lo12(.LCPI11_0)
; LA32-NEXT: xvbitsel.v $xr0, $xr1, $xr0, $xr2
; LA32-NEXT: xvst $xr0, $a0, 0
; LA32-NEXT: ret
;
; LA64-LABEL: select_v4f64:
; LA64: # %bb.0:
; LA64-NEXT: xvld $xr0, $a1, 0
; LA64-NEXT: xvld $xr1, $a2, 0
; LA64-NEXT: pcalau12i $a1, %pc_hi20(.LCPI11_0)
; LA64-NEXT: xvld $xr2, $a1, %pc_lo12(.LCPI11_0)
; LA64-NEXT: xvshuf.d $xr2, $xr1, $xr0
; LA64-NEXT: xvst $xr2, $a0, 0
; LA64-NEXT: ret
%v0 = load <4 x double>, ptr %a0
%v1 = load <4 x double>, ptr %a1
%sel = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x double> %v0, <4 x double> %v1
Expand Down
78 changes: 44 additions & 34 deletions llvm/test/CodeGen/LoongArch/lsx/vselect.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64

define void @select_v16i8_imm(ptr %res, ptr %a0) nounwind {
; CHECK-LABEL: select_v16i8_imm:
Expand Down Expand Up @@ -51,9 +51,7 @@ define void @select_v16i8_1(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: vld $vr0, $a1, 0
; CHECK-NEXT: vld $vr1, $a2, 0
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI3_0)
; CHECK-NEXT: vld $vr2, $a1, %pc_lo12(.LCPI3_0)
; CHECK-NEXT: vbitsel.v $vr0, $vr1, $vr0, $vr2
; CHECK-NEXT: vshuf4i.d $vr0, $vr1, 6
; CHECK-NEXT: vst $vr0, $a0, 0
; CHECK-NEXT: ret
%v0 = load <16 x i8>, ptr %a0
Expand All @@ -70,7 +68,7 @@ define void @select_v16i8_2(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK-NEXT: vld $vr1, $a2, 0
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI4_0)
; CHECK-NEXT: vld $vr2, $a1, %pc_lo12(.LCPI4_0)
; CHECK-NEXT: vbitsel.v $vr0, $vr1, $vr0, $vr2
; CHECK-NEXT: vshuf.b $vr0, $vr1, $vr0, $vr2
; CHECK-NEXT: vst $vr0, $a0, 0
; CHECK-NEXT: ret
%v0 = load <16 x i8>, ptr %a0
Expand Down Expand Up @@ -102,9 +100,7 @@ define void @select_v8i16_1(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: vld $vr0, $a1, 0
; CHECK-NEXT: vld $vr1, $a2, 0
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI6_0)
; CHECK-NEXT: vld $vr2, $a1, %pc_lo12(.LCPI6_0)
; CHECK-NEXT: vbitsel.v $vr0, $vr1, $vr0, $vr2
; CHECK-NEXT: vshuf4i.d $vr0, $vr1, 12
; CHECK-NEXT: vst $vr0, $a0, 0
; CHECK-NEXT: ret
%v0 = load <8 x i16>, ptr %a0
Expand All @@ -121,8 +117,8 @@ define void @select_v8i16_2(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK-NEXT: vld $vr1, $a2, 0
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI7_0)
; CHECK-NEXT: vld $vr2, $a1, %pc_lo12(.LCPI7_0)
; CHECK-NEXT: vbitsel.v $vr0, $vr1, $vr0, $vr2
; CHECK-NEXT: vst $vr0, $a0, 0
; CHECK-NEXT: vshuf.w $vr2, $vr1, $vr0
; CHECK-NEXT: vst $vr2, $a0, 0
; CHECK-NEXT: ret
%v0 = load <8 x i16>, ptr %a0
%v1 = load <8 x i16>, ptr %a1
Expand Down Expand Up @@ -152,9 +148,7 @@ define void @select_v4i32_1(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: vld $vr0, $a1, 0
; CHECK-NEXT: vld $vr1, $a2, 0
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI9_0)
; CHECK-NEXT: vld $vr2, $a1, %pc_lo12(.LCPI9_0)
; CHECK-NEXT: vbitsel.v $vr0, $vr1, $vr0, $vr2
; CHECK-NEXT: vshuf4i.d $vr0, $vr1, 12
; CHECK-NEXT: vst $vr0, $a0, 0
; CHECK-NEXT: ret
%v0 = load <4 x i32>, ptr %a0
Expand All @@ -171,8 +165,8 @@ define void @select_v4f32(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK-NEXT: vld $vr1, $a2, 0
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI10_0)
; CHECK-NEXT: vld $vr2, $a1, %pc_lo12(.LCPI10_0)
; CHECK-NEXT: vbitsel.v $vr0, $vr1, $vr0, $vr2
; CHECK-NEXT: vst $vr0, $a0, 0
; CHECK-NEXT: vshuf.w $vr2, $vr1, $vr0
; CHECK-NEXT: vst $vr2, $a0, 0
; CHECK-NEXT: ret
%v0 = load <4 x float>, ptr %a0
%v1 = load <4 x float>, ptr %a1
Expand All @@ -182,15 +176,23 @@ define void @select_v4f32(ptr %res, ptr %a0, ptr %a1) nounwind {
}

define void @select_v2i64(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK-LABEL: select_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vld $vr0, $a1, 0
; CHECK-NEXT: vld $vr1, $a2, 0
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI11_0)
; CHECK-NEXT: vld $vr2, $a1, %pc_lo12(.LCPI11_0)
; CHECK-NEXT: vbitsel.v $vr0, $vr1, $vr0, $vr2
; CHECK-NEXT: vst $vr0, $a0, 0
; CHECK-NEXT: ret
; LA32-LABEL: select_v2i64:
; LA32: # %bb.0:
; LA32-NEXT: vld $vr0, $a1, 0
; LA32-NEXT: vld $vr1, $a2, 0
; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI11_0)
; LA32-NEXT: vld $vr2, $a1, %pc_lo12(.LCPI11_0)
; LA32-NEXT: vbitsel.v $vr0, $vr1, $vr0, $vr2
; LA32-NEXT: vst $vr0, $a0, 0
; LA32-NEXT: ret
;
; LA64-LABEL: select_v2i64:
; LA64: # %bb.0:
; LA64-NEXT: vld $vr0, $a1, 0
; LA64-NEXT: vld $vr1, $a2, 0
; LA64-NEXT: vshuf4i.d $vr0, $vr1, 12
; LA64-NEXT: vst $vr0, $a0, 0
; LA64-NEXT: ret
%v0 = load <2 x i64>, ptr %a0
%v1 = load <2 x i64>, ptr %a1
%sel = select <2 x i1> <i1 true, i1 false>, <2 x i64> %v0, <2 x i64> %v1
Expand All @@ -199,15 +201,23 @@ define void @select_v2i64(ptr %res, ptr %a0, ptr %a1) nounwind {
}

define void @select_v2f64(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK-LABEL: select_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vld $vr0, $a1, 0
; CHECK-NEXT: vld $vr1, $a2, 0
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI12_0)
; CHECK-NEXT: vld $vr2, $a1, %pc_lo12(.LCPI12_0)
; CHECK-NEXT: vbitsel.v $vr0, $vr1, $vr0, $vr2
; CHECK-NEXT: vst $vr0, $a0, 0
; CHECK-NEXT: ret
; LA32-LABEL: select_v2f64:
; LA32: # %bb.0:
; LA32-NEXT: vld $vr0, $a1, 0
; LA32-NEXT: vld $vr1, $a2, 0
; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI12_0)
; LA32-NEXT: vld $vr2, $a1, %pc_lo12(.LCPI12_0)
; LA32-NEXT: vbitsel.v $vr0, $vr1, $vr0, $vr2
; LA32-NEXT: vst $vr0, $a0, 0
; LA32-NEXT: ret
;
; LA64-LABEL: select_v2f64:
; LA64: # %bb.0:
; LA64-NEXT: vld $vr0, $a1, 0
; LA64-NEXT: vld $vr1, $a2, 0
; LA64-NEXT: vshuf4i.d $vr0, $vr1, 6
; LA64-NEXT: vst $vr0, $a0, 0
; LA64-NEXT: ret
%v0 = load <2 x double>, ptr %a0
%v1 = load <2 x double>, ptr %a1
%sel = select <2 x i1> <i1 false, i1 true>, <2 x double> %v0, <2 x double> %v1
Expand Down