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[RISCV] Don't transfer (select c, t, f) to Zicond when optimizing for size #163501

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[RISCV] Don't transfer (select c, t, f) to Zicond when optimizing for size #163501

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In general, there is no code size issue when the branch version
(branch+mv+mv) is replaced with the Zicond version
(czero.nez+czero.eqz+or), as both contain 3 instructions. However, if the
cond of select is shared by multiple select instructions, fewer
instructions are required (they can share the same comparision
instruction) when using branch rather than Zicond. We add the checking
whether CondV has one use when optimizing for size.

Fixes #158633.

@tclin914
[RISCV] Pre-commit
8721e00
@tclin914
[RISCV] Don't transfer (select c, t, f) to Zicond when optimizing for…
f916782 
… size

In general, there is no code size issue when the branch version
(branch+mv+mv) is replaced with the Zicond version
(czero.nez+czero.eqz+or), as both contain 3 instructions. However, if the
cond of select is shared by multiple select instructions, fewer
instructions are required (they can share the same comparision
instruction) when using branch rather than Zicond. We add the checking
whether CondV has one use when optimizing for size.

Fixes llvm#158633.
@tclin914 tclin914 requested review from preames and topperc October 15, 2025 05:31
@llvmbot
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llvmbot commented Oct 15, 2025

@llvm/pr-subscribers-backend-risc-v

Author: Jim Lin (tclin914)

Changes

In general, there is no code size issue when the branch version
(branch+mv+mv) is replaced with the Zicond version
(czero.nez+czero.eqz+or), as both contain 3 instructions. However, if the
cond of select is shared by multiple select instructions, fewer
instructions are required (they can share the same comparision
instruction) when using branch rather than Zicond. We add the checking
whether CondV has one use when optimizing for size.

Fixes #158633.

Patch is 34.89 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/163501.diff

2 Files Affected:

  • (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+5-2)
  • (modified) llvm/test/CodeGen/RISCV/condops.ll (+228-162)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 7123a2d706787..c334caf5f50f8 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -9458,8 +9458,11 @@ SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
     }
 
     // (select c, t, f) -> (or (czero_eqz t, c), (czero_nez f, c))
-    // Unless we have the short forward branch optimization.
-    if (!Subtarget.hasConditionalMoveFusion())
+    // Unless we have the short forward branch optimization or CondV has one use
+    // when optimizaing for size.
+    if (!Subtarget.hasConditionalMoveFusion() &&
+        (!DAG.shouldOptForSize() ||
+         (DAG.shouldOptForSize() && CondV.hasOneUse())))
       return DAG.getNode(
           ISD::OR, DL, VT,
           DAG.getNode(RISCVISD::CZERO_EQZ, DL, VT, TrueV, CondV),
diff --git a/llvm/test/CodeGen/RISCV/condops.ll b/llvm/test/CodeGen/RISCV/condops.ll
index 9d95f1f5c9615..5ef4b7572e23b 100644
--- a/llvm/test/CodeGen/RISCV/condops.ll
+++ b/llvm/test/CodeGen/RISCV/condops.ll
@@ -1341,6 +1341,72 @@ define i64 @basic(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
   ret i64 %sel
 }
 
+define i64 @basic_optsize(i1 zeroext %rc, i64 %rs1, i64 %rs2) optsize {
+; RV32I-LABEL: basic_optsize:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    bnez a0, .LBB23_2
+; RV32I-NEXT:  # %bb.1:
+; RV32I-NEXT:    mv a1, a3
+; RV32I-NEXT:    mv a2, a4
+; RV32I-NEXT:  .LBB23_2:
+; RV32I-NEXT:    mv a0, a1
+; RV32I-NEXT:    mv a1, a2
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: basic_optsize:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    bnez a0, .LBB23_2
+; RV64I-NEXT:  # %bb.1:
+; RV64I-NEXT:    mv a1, a2
+; RV64I-NEXT:  .LBB23_2:
+; RV64I-NEXT:    mv a0, a1
+; RV64I-NEXT:    ret
+;
+; RV32XVENTANACONDOPS-LABEL: basic_optsize:
+; RV32XVENTANACONDOPS:       # %bb.0:
+; RV32XVENTANACONDOPS-NEXT:    bnez a0, .LBB23_2
+; RV32XVENTANACONDOPS-NEXT:  # %bb.1:
+; RV32XVENTANACONDOPS-NEXT:    mv a1, a3
+; RV32XVENTANACONDOPS-NEXT:    mv a2, a4
+; RV32XVENTANACONDOPS-NEXT:  .LBB23_2:
+; RV32XVENTANACONDOPS-NEXT:    mv a0, a1
+; RV32XVENTANACONDOPS-NEXT:    mv a1, a2
+; RV32XVENTANACONDOPS-NEXT:    ret
+;
+; RV64XVENTANACONDOPS-LABEL: basic_optsize:
+; RV64XVENTANACONDOPS:       # %bb.0:
+; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a2, a2, a0
+; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a1, a0
+; RV64XVENTANACONDOPS-NEXT:    or a0, a0, a2
+; RV64XVENTANACONDOPS-NEXT:    ret
+;
+; RV64XTHEADCONDMOV-LABEL: basic_optsize:
+; RV64XTHEADCONDMOV:       # %bb.0:
+; RV64XTHEADCONDMOV-NEXT:    th.mveqz a1, a2, a0
+; RV64XTHEADCONDMOV-NEXT:    mv a0, a1
+; RV64XTHEADCONDMOV-NEXT:    ret
+;
+; RV32ZICOND-LABEL: basic_optsize:
+; RV32ZICOND:       # %bb.0:
+; RV32ZICOND-NEXT:    bnez a0, .LBB23_2
+; RV32ZICOND-NEXT:  # %bb.1:
+; RV32ZICOND-NEXT:    mv a1, a3
+; RV32ZICOND-NEXT:    mv a2, a4
+; RV32ZICOND-NEXT:  .LBB23_2:
+; RV32ZICOND-NEXT:    mv a0, a1
+; RV32ZICOND-NEXT:    mv a1, a2
+; RV32ZICOND-NEXT:    ret
+;
+; RV64ZICOND-LABEL: basic_optsize:
+; RV64ZICOND:       # %bb.0:
+; RV64ZICOND-NEXT:    czero.nez a2, a2, a0
+; RV64ZICOND-NEXT:    czero.eqz a0, a1, a0
+; RV64ZICOND-NEXT:    or a0, a0, a2
+; RV64ZICOND-NEXT:    ret
+  %sel = select i1 %rc, i64 %rs1, i64 %rs2
+  ret i64 %sel
+}
+
 define i64 @seteq(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 ; RV32I-LABEL: seteq:
 ; RV32I:       # %bb.0:
@@ -1348,20 +1414,20 @@ define i64 @seteq(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 ; RV32I-NEXT:    xor a0, a0, a2
 ; RV32I-NEXT:    or a1, a0, a1
 ; RV32I-NEXT:    mv a0, a4
-; RV32I-NEXT:    beqz a1, .LBB23_2
+; RV32I-NEXT:    beqz a1, .LBB24_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a0, a6
 ; RV32I-NEXT:    mv a5, a7
-; RV32I-NEXT:  .LBB23_2:
+; RV32I-NEXT:  .LBB24_2:
 ; RV32I-NEXT:    mv a1, a5
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: seteq:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    beq a0, a1, .LBB23_2
+; RV64I-NEXT:    beq a0, a1, .LBB24_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a2, a3
-; RV64I-NEXT:  .LBB23_2:
+; RV64I-NEXT:  .LBB24_2:
 ; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:    ret
 ;
@@ -1425,20 +1491,20 @@ define i64 @setne(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 ; RV32I-NEXT:    xor a0, a0, a2
 ; RV32I-NEXT:    or a1, a0, a1
 ; RV32I-NEXT:    mv a0, a4
-; RV32I-NEXT:    bnez a1, .LBB24_2
+; RV32I-NEXT:    bnez a1, .LBB25_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a0, a6
 ; RV32I-NEXT:    mv a5, a7
-; RV32I-NEXT:  .LBB24_2:
+; RV32I-NEXT:  .LBB25_2:
 ; RV32I-NEXT:    mv a1, a5
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: setne:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    bne a0, a1, .LBB24_2
+; RV64I-NEXT:    bne a0, a1, .LBB25_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a2, a3
-; RV64I-NEXT:  .LBB24_2:
+; RV64I-NEXT:  .LBB25_2:
 ; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:    ret
 ;
@@ -1498,28 +1564,28 @@ define i64 @setne(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 define i64 @setgt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 ; RV32I-LABEL: setgt:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    beq a1, a3, .LBB25_2
+; RV32I-NEXT:    beq a1, a3, .LBB26_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    slt a0, a3, a1
-; RV32I-NEXT:    beqz a0, .LBB25_3
-; RV32I-NEXT:    j .LBB25_4
-; RV32I-NEXT:  .LBB25_2:
+; RV32I-NEXT:    beqz a0, .LBB26_3
+; RV32I-NEXT:    j .LBB26_4
+; RV32I-NEXT:  .LBB26_2:
 ; RV32I-NEXT:    sltu a0, a2, a0
-; RV32I-NEXT:    bnez a0, .LBB25_4
-; RV32I-NEXT:  .LBB25_3:
+; RV32I-NEXT:    bnez a0, .LBB26_4
+; RV32I-NEXT:  .LBB26_3:
 ; RV32I-NEXT:    mv a4, a6
 ; RV32I-NEXT:    mv a5, a7
-; RV32I-NEXT:  .LBB25_4:
+; RV32I-NEXT:  .LBB26_4:
 ; RV32I-NEXT:    mv a0, a4
 ; RV32I-NEXT:    mv a1, a5
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: setgt:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    blt a1, a0, .LBB25_2
+; RV64I-NEXT:    blt a1, a0, .LBB26_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a2, a3
-; RV64I-NEXT:  .LBB25_2:
+; RV64I-NEXT:  .LBB26_2:
 ; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:    ret
 ;
@@ -1585,28 +1651,28 @@ define i64 @setgt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 define i64 @setge(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 ; RV32I-LABEL: setge:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    beq a1, a3, .LBB26_2
+; RV32I-NEXT:    beq a1, a3, .LBB27_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    slt a0, a1, a3
-; RV32I-NEXT:    bnez a0, .LBB26_3
-; RV32I-NEXT:    j .LBB26_4
-; RV32I-NEXT:  .LBB26_2:
+; RV32I-NEXT:    bnez a0, .LBB27_3
+; RV32I-NEXT:    j .LBB27_4
+; RV32I-NEXT:  .LBB27_2:
 ; RV32I-NEXT:    sltu a0, a0, a2
-; RV32I-NEXT:    beqz a0, .LBB26_4
-; RV32I-NEXT:  .LBB26_3:
+; RV32I-NEXT:    beqz a0, .LBB27_4
+; RV32I-NEXT:  .LBB27_3:
 ; RV32I-NEXT:    mv a4, a6
 ; RV32I-NEXT:    mv a5, a7
-; RV32I-NEXT:  .LBB26_4:
+; RV32I-NEXT:  .LBB27_4:
 ; RV32I-NEXT:    mv a0, a4
 ; RV32I-NEXT:    mv a1, a5
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: setge:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    bge a0, a1, .LBB26_2
+; RV64I-NEXT:    bge a0, a1, .LBB27_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a2, a3
-; RV64I-NEXT:  .LBB26_2:
+; RV64I-NEXT:  .LBB27_2:
 ; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:    ret
 ;
@@ -1672,28 +1738,28 @@ define i64 @setge(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 define i64 @setlt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 ; RV32I-LABEL: setlt:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    beq a1, a3, .LBB27_2
+; RV32I-NEXT:    beq a1, a3, .LBB28_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    slt a0, a1, a3
-; RV32I-NEXT:    beqz a0, .LBB27_3
-; RV32I-NEXT:    j .LBB27_4
-; RV32I-NEXT:  .LBB27_2:
+; RV32I-NEXT:    beqz a0, .LBB28_3
+; RV32I-NEXT:    j .LBB28_4
+; RV32I-NEXT:  .LBB28_2:
 ; RV32I-NEXT:    sltu a0, a0, a2
-; RV32I-NEXT:    bnez a0, .LBB27_4
-; RV32I-NEXT:  .LBB27_3:
+; RV32I-NEXT:    bnez a0, .LBB28_4
+; RV32I-NEXT:  .LBB28_3:
 ; RV32I-NEXT:    mv a4, a6
 ; RV32I-NEXT:    mv a5, a7
-; RV32I-NEXT:  .LBB27_4:
+; RV32I-NEXT:  .LBB28_4:
 ; RV32I-NEXT:    mv a0, a4
 ; RV32I-NEXT:    mv a1, a5
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: setlt:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    blt a0, a1, .LBB27_2
+; RV64I-NEXT:    blt a0, a1, .LBB28_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a2, a3
-; RV64I-NEXT:  .LBB27_2:
+; RV64I-NEXT:  .LBB28_2:
 ; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:    ret
 ;
@@ -1759,28 +1825,28 @@ define i64 @setlt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 define i64 @setle(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 ; RV32I-LABEL: setle:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    beq a1, a3, .LBB28_2
+; RV32I-NEXT:    beq a1, a3, .LBB29_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    slt a0, a3, a1
-; RV32I-NEXT:    bnez a0, .LBB28_3
-; RV32I-NEXT:    j .LBB28_4
-; RV32I-NEXT:  .LBB28_2:
+; RV32I-NEXT:    bnez a0, .LBB29_3
+; RV32I-NEXT:    j .LBB29_4
+; RV32I-NEXT:  .LBB29_2:
 ; RV32I-NEXT:    sltu a0, a2, a0
-; RV32I-NEXT:    beqz a0, .LBB28_4
-; RV32I-NEXT:  .LBB28_3:
+; RV32I-NEXT:    beqz a0, .LBB29_4
+; RV32I-NEXT:  .LBB29_3:
 ; RV32I-NEXT:    mv a4, a6
 ; RV32I-NEXT:    mv a5, a7
-; RV32I-NEXT:  .LBB28_4:
+; RV32I-NEXT:  .LBB29_4:
 ; RV32I-NEXT:    mv a0, a4
 ; RV32I-NEXT:    mv a1, a5
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: setle:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    bge a1, a0, .LBB28_2
+; RV64I-NEXT:    bge a1, a0, .LBB29_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a2, a3
-; RV64I-NEXT:  .LBB28_2:
+; RV64I-NEXT:  .LBB29_2:
 ; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:    ret
 ;
@@ -1846,28 +1912,28 @@ define i64 @setle(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 define i64 @setugt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 ; RV32I-LABEL: setugt:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    beq a1, a3, .LBB29_2
+; RV32I-NEXT:    beq a1, a3, .LBB30_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    sltu a0, a3, a1
-; RV32I-NEXT:    beqz a0, .LBB29_3
-; RV32I-NEXT:    j .LBB29_4
-; RV32I-NEXT:  .LBB29_2:
+; RV32I-NEXT:    beqz a0, .LBB30_3
+; RV32I-NEXT:    j .LBB30_4
+; RV32I-NEXT:  .LBB30_2:
 ; RV32I-NEXT:    sltu a0, a2, a0
-; RV32I-NEXT:    bnez a0, .LBB29_4
-; RV32I-NEXT:  .LBB29_3:
+; RV32I-NEXT:    bnez a0, .LBB30_4
+; RV32I-NEXT:  .LBB30_3:
 ; RV32I-NEXT:    mv a4, a6
 ; RV32I-NEXT:    mv a5, a7
-; RV32I-NEXT:  .LBB29_4:
+; RV32I-NEXT:  .LBB30_4:
 ; RV32I-NEXT:    mv a0, a4
 ; RV32I-NEXT:    mv a1, a5
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: setugt:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    bltu a1, a0, .LBB29_2
+; RV64I-NEXT:    bltu a1, a0, .LBB30_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a2, a3
-; RV64I-NEXT:  .LBB29_2:
+; RV64I-NEXT:  .LBB30_2:
 ; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:    ret
 ;
@@ -1933,28 +1999,28 @@ define i64 @setugt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 define i64 @setuge(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 ; RV32I-LABEL: setuge:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    beq a1, a3, .LBB30_2
+; RV32I-NEXT:    beq a1, a3, .LBB31_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    sltu a0, a1, a3
-; RV32I-NEXT:    bnez a0, .LBB30_3
-; RV32I-NEXT:    j .LBB30_4
-; RV32I-NEXT:  .LBB30_2:
+; RV32I-NEXT:    bnez a0, .LBB31_3
+; RV32I-NEXT:    j .LBB31_4
+; RV32I-NEXT:  .LBB31_2:
 ; RV32I-NEXT:    sltu a0, a0, a2
-; RV32I-NEXT:    beqz a0, .LBB30_4
-; RV32I-NEXT:  .LBB30_3:
+; RV32I-NEXT:    beqz a0, .LBB31_4
+; RV32I-NEXT:  .LBB31_3:
 ; RV32I-NEXT:    mv a4, a6
 ; RV32I-NEXT:    mv a5, a7
-; RV32I-NEXT:  .LBB30_4:
+; RV32I-NEXT:  .LBB31_4:
 ; RV32I-NEXT:    mv a0, a4
 ; RV32I-NEXT:    mv a1, a5
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: setuge:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    bgeu a0, a1, .LBB30_2
+; RV64I-NEXT:    bgeu a0, a1, .LBB31_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a2, a3
-; RV64I-NEXT:  .LBB30_2:
+; RV64I-NEXT:  .LBB31_2:
 ; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:    ret
 ;
@@ -2020,28 +2086,28 @@ define i64 @setuge(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 define i64 @setult(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 ; RV32I-LABEL: setult:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    beq a1, a3, .LBB31_2
+; RV32I-NEXT:    beq a1, a3, .LBB32_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    sltu a0, a1, a3
-; RV32I-NEXT:    beqz a0, .LBB31_3
-; RV32I-NEXT:    j .LBB31_4
-; RV32I-NEXT:  .LBB31_2:
+; RV32I-NEXT:    beqz a0, .LBB32_3
+; RV32I-NEXT:    j .LBB32_4
+; RV32I-NEXT:  .LBB32_2:
 ; RV32I-NEXT:    sltu a0, a0, a2
-; RV32I-NEXT:    bnez a0, .LBB31_4
-; RV32I-NEXT:  .LBB31_3:
+; RV32I-NEXT:    bnez a0, .LBB32_4
+; RV32I-NEXT:  .LBB32_3:
 ; RV32I-NEXT:    mv a4, a6
 ; RV32I-NEXT:    mv a5, a7
-; RV32I-NEXT:  .LBB31_4:
+; RV32I-NEXT:  .LBB32_4:
 ; RV32I-NEXT:    mv a0, a4
 ; RV32I-NEXT:    mv a1, a5
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: setult:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    bltu a0, a1, .LBB31_2
+; RV64I-NEXT:    bltu a0, a1, .LBB32_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a2, a3
-; RV64I-NEXT:  .LBB31_2:
+; RV64I-NEXT:  .LBB32_2:
 ; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:    ret
 ;
@@ -2107,28 +2173,28 @@ define i64 @setult(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 define i64 @setule(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
 ; RV32I-LABEL: setule:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    beq a1, a3, .LBB32_2
+; RV32I-NEXT:    beq a1, a3, .LBB33_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    sltu a0, a3, a1
-; RV32I-NEXT:    bnez a0, .LBB32_3
-; RV32I-NEXT:    j .LBB32_4
-; RV32I-NEXT:  .LBB32_2:
+; RV32I-NEXT:    bnez a0, .LBB33_3
+; RV32I-NEXT:    j .LBB33_4
+; RV32I-NEXT:  .LBB33_2:
 ; RV32I-NEXT:    sltu a0, a2, a0
-; RV32I-NEXT:    beqz a0, .LBB32_4
-; RV32I-NEXT:  .LBB32_3:
+; RV32I-NEXT:    beqz a0, .LBB33_4
+; RV32I-NEXT:  .LBB33_3:
 ; RV32I-NEXT:    mv a4, a6
 ; RV32I-NEXT:    mv a5, a7
-; RV32I-NEXT:  .LBB32_4:
+; RV32I-NEXT:  .LBB33_4:
 ; RV32I-NEXT:    mv a0, a4
 ; RV32I-NEXT:    mv a1, a5
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: setule:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    bgeu a1, a0, .LBB32_2
+; RV64I-NEXT:    bgeu a1, a0, .LBB33_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a2, a3
-; RV64I-NEXT:  .LBB32_2:
+; RV64I-NEXT:  .LBB33_2:
 ; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:    ret
 ;
@@ -2196,20 +2262,20 @@ define i64 @seteq_zero(i64 %a, i64 %rs1, i64 %rs2) {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    or a1, a0, a1
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    beqz a1, .LBB33_2
+; RV32I-NEXT:    beqz a1, .LBB34_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a0, a4
 ; RV32I-NEXT:    mv a3, a5
-; RV32I-NEXT:  .LBB33_2:
+; RV32I-NEXT:  .LBB34_2:
 ; RV32I-NEXT:    mv a1, a3
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: seteq_zero:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    beqz a0, .LBB33_2
+; RV64I-NEXT:    beqz a0, .LBB34_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a1, a2
-; RV64I-NEXT:  .LBB33_2:
+; RV64I-NEXT:  .LBB34_2:
 ; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:    ret
 ;
@@ -2264,20 +2330,20 @@ define i64 @setne_zero(i64 %a, i64 %rs1, i64 %rs2) {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    or a1, a0, a1
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    bnez a1, .LBB34_2
+; RV32I-NEXT:    bnez a1, .LBB35_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a0, a4
 ; RV32I-NEXT:    mv a3, a5
-; RV32I-NEXT:  .LBB34_2:
+; RV32I-NEXT:  .LBB35_2:
 ; RV32I-NEXT:    mv a1, a3
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: setne_zero:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    bnez a0, .LBB34_2
+; RV64I-NEXT:    bnez a0, .LBB35_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a1, a2
-; RV64I-NEXT:  .LBB34_2:
+; RV64I-NEXT:  .LBB35_2:
 ; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:    ret
 ;
@@ -2333,21 +2399,21 @@ define i64 @seteq_constant(i64 %a, i64 %rs1, i64 %rs2) {
 ; RV32I-NEXT:    xori a0, a0, 123
 ; RV32I-NEXT:    or a1, a0, a1
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    beqz a1, .LBB35_2
+; RV32I-NEXT:    beqz a1, .LBB36_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a0, a4
 ; RV32I-NEXT:    mv a3, a5
-; RV32I-NEXT:  .LBB35_2:
+; RV32I-NEXT:  .LBB36_2:
 ; RV32I-NEXT:    mv a1, a3
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: seteq_constant:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a3, 123
-; RV64I-NEXT:    beq a0, a3, .LBB35_2
+; RV64I-NEXT:    beq a0, a3, .LBB36_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a1, a2
-; RV64I-NEXT:  .LBB35_2:
+; RV64I-NEXT:  .LBB36_2:
 ; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:    ret
 ;
@@ -2408,21 +2474,21 @@ define i64 @setne_constant(i64 %a, i64 %rs1, i64 %rs2) {
 ; RV32I-NEXT:    xori a0, a0, 456
 ; RV32I-NEXT:    or a1, a0, a1
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    bnez a1, .LBB36_2
+; RV32I-NEXT:    bnez a1, .LBB37_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a0, a4
 ; RV32I-NEXT:    mv a3, a5
-; RV32I-NEXT:  .LBB36_2:
+; RV32I-NEXT:  .LBB37_2:
 ; RV32I-NEXT:    mv a1, a3
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: setne_constant:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a3, 456
-; RV64I-NEXT:    bne a0, a3, .LBB36_2
+; RV64I-NEXT:    bne a0, a3, .LBB37_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a1, a2
-; RV64I-NEXT:  .LBB36_2:
+; RV64I-NEXT:  .LBB37_2:
 ; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:    ret
 ;
@@ -2483,21 +2549,21 @@ define i64 @seteq_2048(i64 %a, i64 %rs1, i64 %rs2) {
 ; RV32I-NEXT:    binvi a0, a0, 11
 ; RV32I-NEXT:    or a1, a0, a1
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    beqz a1, .LBB37_2
+; RV32I-NEXT:    beqz a1, .LBB38_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a0, a4
 ; RV32I-NEXT:    mv a3, a5
-; RV32I-NEXT:  .LBB37_2:
+; RV32I-NEXT:  .LBB38_2:
 ; RV32I-NEXT:    mv a1, a3
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: seteq_2048:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    bseti a3, zero, 11
-; RV64I-NEXT:    beq a0, a3, .LBB37_2
+; RV64I-NEXT:    beq a0, a3, .LBB38_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a1, a2
-; RV64I-NEXT:  .LBB37_2:
+; RV64I-NEXT:  .LBB38_2:
 ; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:    ret
 ;
@@ -2559,21 +2625,21 @@ define i64 @seteq_neg2048(i64 %a, i64 %rs1, i64 %rs2) {
 ; RV32I-NEXT:    xori a0, a0, -2048
 ; RV32I-NEXT:    or a1, a0, a1
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    beqz a1, .LBB38_2
+; RV32I-NEXT:    beqz a1, .LBB39_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a0, a4
 ; RV32I-NEXT:    mv a3, a5
-; RV32I-NEXT:  .LBB38_2:
+; RV32I-NEXT:  .LBB39_2:
 ; RV32I-NEXT:    mv a1, a3
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: seteq_neg2048:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a3, -2048
-; RV64I-NEXT:    beq a0, a3, .LBB38_2
+; RV64I-NEXT:    beq a0, a3, .LBB39_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a1, a2
-; RV64I-NEXT:  .LBB38_2:
+; RV64I-NEXT:  .LBB39_2:
 ; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:    ret
 ;
@@ -2637,21 +2703,21 @@ define i64 @setne_neg2048(i64 %a, i64 %rs1, i64 %rs2) {
 ; RV32I-NEXT:    xori a0, a0, -2048
 ; RV32I-NEXT:    or a1, a0, a1
 ; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    bnez a1, .LBB39_2
+; RV32I-NEXT:    bnez a1, .LBB40_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a0, a4
 ; RV32I-NEXT:    mv a3, a5
-; RV32I-NEXT:  .LBB39_2:
+; RV32I-NEXT:  .LBB40_2:
 ; RV32I-NEXT:    mv a1, a3
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: setne_neg2048:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a3, -2048
-; RV64I-NEXT:    bne a0, a3, .LBB39_2
+; RV64I-NEXT:    bne a0, a3, .LBB40_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a1, a2
-; RV64I-NEXT:  .LBB39_2:
+; RV64I-NEXT:  .LBB40_2:
 ; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:    ret
 ;
@@ -3649,12 +3715,12 @@ define void @sextw_removal_maskc(i1 %c, i32 signext %arg, i32 signext %arg1) nou
 ; RV32I-NEXT:    slli a0, a0, 31
 ; RV32I-NEXT:    srai a0, a0, 31
 ; RV32I-NEXT:    and s1, a0, a1
-; RV32I-NEXT:  .LBB56_1: # %bb2
+; RV32I-NEXT:  .LBB57_1: # %bb2
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    call bar
 ; RV32I-NEXT:    sll s1, s1, s0
-; RV32I-NEXT:    bnez a0, .LBB56_1
+; RV32I-NEXT:    bnez a0, .LBB57_1
 ; RV32I-NEXT:  # %bb.2: # %bb7
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
@@ -3672,12 +3738,12 @@ define void @sextw_removal_maskc(i1 %c, i32 signext %arg, i32 signext %arg1) nou
 ; RV64I-NEXT:    slli a0, a0, 63
 ; RV64I-NEXT:    srai a0, a0, 63
 ; RV64I-NEXT:    and s1, a0, a1
-; RV64I-NEXT:  .LBB56_1: # %bb2
+; RV64I-NEXT:  .LBB57_1: # %bb2
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    call bar
 ; RV64I-NEXT:    sllw s1, s1, s0
-; RV64I-NEXT:    bnez a0, .LBB56_1
+; RV64I-NEXT:    bnez a0, .LBB57_1
 ; RV64I-NEXT:  # %bb.2: # %bb7
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
@@ -3694,12 +3760,12 @@ define void @sextw_removal_maskc(i1 %c, i32 signext %arg,...
[truncated]

mshockwave
mshockwave reviewed Oct 15, 2025
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[RISC-V] Zicond increases static code size even with -Oz

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@tclin914 @llvmbot @mshockwave