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[ROCDL] Added asynccnt and tensorcnt wait ops (gfx1250) #163533

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Merged
merged 1 commit into from
Oct 15, 2025
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[ROCDL] Added asynccnt and tensorcnt wait ops (gfx1250) #163533

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26 changes: 26 additions & 0 deletions mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
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Original file line number Diff line number Diff line change
Expand Up @@ -412,6 +412,32 @@ def ROCDL_WaitExpcntOp: ROCDL_ConcreteNonMemIntrOp<"s.wait.expcnt", [], 0, [0],
let assemblyFormat = "$count attr-dict";
}

def ROCDL_WaitAsynccntOp: ROCDL_ConcreteNonMemIntrOp<"s.wait.asynccnt", [], 0, [0], ["count"]>,
Arguments<(ins I16Attr:$count)> {
let summary = "Wait until ASYNCCNT is less than or equal to `count`";
let description = [{
Wait for the counter specified to be less-than or equal-to the `count`
before continuing.

Available on gfx1250+.
}];
let results = (outs);
let assemblyFormat = "$count attr-dict";
}

def ROCDL_WaitTensorcntOp: ROCDL_ConcreteNonMemIntrOp<"s.wait.tensorcnt", [], 0, [0], ["count"]>,
Arguments<(ins I16Attr:$count)> {
let summary = "Wait until TENSORCNT is less than or equal to `count`";
let description = [{
Wait for the counter specified to be less-than or equal-to the `count`
before continuing.

Available on gfx1250+.
}];
let results = (outs);
let assemblyFormat = "$count attr-dict";
}

def ROCDL_SetPrioOp : ROCDL_ConcreteNonMemIntrOp<"s.setprio", [], 0, [0], ["priority"]>,
Arguments<(ins I16Attr:$priority)> {
let assemblyFormat = "$priority attr-dict";
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14 changes: 14 additions & 0 deletions mlir/test/Dialect/LLVMIR/rocdl.mlir
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Expand Up @@ -1035,6 +1035,20 @@ llvm.func @rocdl.s.wait.expcnt() {
llvm.return
}

llvm.func @rocdl.s.wait.asynccnt() {
// CHECK-LABEL: rocdl.s.wait.asynccnt
// CHECK: rocdl.s.wait.asynccnt 0
rocdl.s.wait.asynccnt 0
llvm.return
}

llvm.func @rocdl.s.wait.tensorcnt() {
// CHECK-LABEL: rocdl.s.wait.tensorcnt
// CHECK: rocdl.s.wait.tensorcnt 0
rocdl.s.wait.tensorcnt 0
llvm.return
}

// -----

llvm.func @rocdl.readfirstlane(%src : f32) -> f32 {
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14 changes: 14 additions & 0 deletions mlir/test/Target/LLVMIR/rocdl.mlir
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Expand Up @@ -276,6 +276,20 @@ llvm.func @rocdl.s.wait.expcnt() {
llvm.return
}

llvm.func @rocdl.s.wait.asynccnt() {
// CHECK-LABEL: rocdl.s.wait.asynccnt
// CHECK-NEXT: call void @llvm.amdgcn.s.wait.asynccnt(i16 0)
rocdl.s.wait.asynccnt 0
llvm.return
}

llvm.func @rocdl.s.wait.tensorcnt() {
// CHECK-LABEL: rocdl.s.wait.tensorcnt
// CHECK-NEXT: call void @llvm.amdgcn.s.wait.tensorcnt(i16 0)
rocdl.s.wait.tensorcnt 0
llvm.return
}

llvm.func @rocdl.setprio() {
// CHECK: call void @llvm.amdgcn.s.setprio(i16 0)
rocdl.s.setprio 0
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