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[LoongArch] Custom legalize vector_shuffle to vextrins #164067

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88 changes: 88 additions & 0 deletions llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1948,6 +1948,91 @@ static SDValue lowerVECTOR_SHUFFLE_VPICKOD(const SDLoc &DL, ArrayRef<int> Mask,
return DAG.getNode(LoongArchISD::VPICKOD, DL, VT, V2, V1);
}

/// Lower VECTOR_SHUFFLE into VEXTRINS (if possible).
///
/// VEXTRINS copies one element of a vector into any place of the result
/// vector and makes no change to the rest elements of the result vector.
///
/// It is possible to lower into VEXTRINS when the mask takes the form:
/// <0, 1, 2, ..., n+i, ..., n-1> or <n, n+1, n+2, ..., i, ..., 2n-1> or
/// <0, 1, 2, ..., i, ..., n-1> or <n, n+1, n+2, ..., n+i, ..., 2n-1>
/// where n is the number of elements in the vector and i is in [0, n).
/// For example:
/// <0, 1, 2, 3, 4, 5, 6, 8> , <2, 9, 10, 11, 12, 13, 14, 15> ,
/// <0, 1, 2, 6, 4, 5, 6, 7> , <8, 9, 10, 11, 12, 9, 14, 15>
///
/// When undef's appear in the mask they are treated as if they were whatever
/// value is necessary in order to fit the above forms.
static SDValue
lowerVECTOR_SHUFFLE_VEXTRINS(const SDLoc &DL, ArrayRef<int> Mask, MVT VT,
SDValue V1, SDValue V2, SelectionDAG &DAG,
const LoongArchSubtarget &Subtarget) {
unsigned NumElts = VT.getVectorNumElements();
MVT EltVT = VT.getVectorElementType();
MVT GRLenVT = Subtarget.getGRLenVT();

if (Mask.size() != NumElts)
return SDValue();

auto tryLowerToExtrAndIns = [&](unsigned Base) -> SDValue {
int DiffCount = 0;
int DiffPos = -1;
for (unsigned i = 0; i < NumElts; ++i) {
if (Mask[i] == -1)
continue;
if (Mask[i] != int(Base + i)) {
++DiffCount;
DiffPos = int(i);
if (DiffCount > 1)
return SDValue();
}
}

// Need exactly one differing element to lower into VEXTRINS.
if (DiffCount != 1)
return SDValue();

// DiffMask must be in [0, 2N).
int DiffMask = Mask[DiffPos];
if (DiffMask < 0 || DiffMask >= int(2 * NumElts))
return SDValue();

// Determine source vector and source index.
SDValue SrcVec;
unsigned SrcIdx;
if (unsigned(DiffMask) < NumElts) {
SrcVec = V1;
SrcIdx = unsigned(DiffMask);
} else {
SrcVec = V2;
SrcIdx = unsigned(DiffMask) - NumElts;
}

// Replace with EXTRACT_VECTOR_ELT + INSERT_VECTOR_ELT, it will match the
// patterns of VEXTRINS in tablegen.
bool IsEltFP = EltVT.isFloatingPoint();
SDValue Extracted =
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IsEltFP ? EltVT : GRLenVT,
SrcVec, DAG.getConstant(SrcIdx, DL, GRLenVT));

SDValue InsertVal = Extracted;
if (!IsEltFP && EltVT != GRLenVT)
InsertVal = DAG.getNode(ISD::ANY_EXTEND, DL, GRLenVT,
DAG.getNode(ISD::TRUNCATE, DL, EltVT, Extracted));

SDValue Result =
DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, (Base == 0) ? V1 : V2,
InsertVal, DAG.getConstant(DiffPos, DL, GRLenVT));

return Result;
};

// Try [0, n-1) insertion then [n, 2n-1) insertion.
if (SDValue Result = tryLowerToExtrAndIns(0))
return Result;
return tryLowerToExtrAndIns(NumElts);
}

/// Lower VECTOR_SHUFFLE into VSHUF.
///
/// This mostly consists of converting the shuffle mask into a BUILD_VECTOR and
Expand Down Expand Up @@ -2028,6 +2113,9 @@ static SDValue lower128BitShuffle(const SDLoc &DL, ArrayRef<int> Mask, MVT VT,
(Result =
lowerVECTOR_SHUFFLE_VSHUF4I(DL, Mask, VT, V1, V2, DAG, Subtarget)))
return Result;
if ((Result =
lowerVECTOR_SHUFFLE_VEXTRINS(DL, Mask, VT, V1, V2, DAG, Subtarget)))
return Result;
if ((Result = lowerVECTOR_SHUFFLEAsZeroOrAnyExtend(DL, Mask, VT, V1, V2, DAG,
Zeroable)))
return Result;
Expand Down
48 changes: 24 additions & 24 deletions llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vextrins.ll
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Original file line number Diff line number Diff line change
@@ -1,16 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx %s -o - | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx %s -o - | FileCheck %s
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx %s -o - | FileCheck %s --check-prefixes=CHECK,LA32
; RUN: llc --mtriple=loongarch64 --mattr=+lsx %s -o - | FileCheck %s --check-prefixes=CHECK,LA64

;; vextrins.b
define void @shufflevector_v16i8(ptr %res, ptr %a, ptr %b) nounwind {
; CHECK-LABEL: shufflevector_v16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vld $vr0, $a1, 0
; CHECK-NEXT: vld $vr1, $a2, 0
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI0_0)
; CHECK-NEXT: vld $vr2, $a1, %pc_lo12(.LCPI0_0)
; CHECK-NEXT: vshuf.b $vr0, $vr1, $vr0, $vr2
; CHECK-NEXT: vextrins.b $vr0, $vr1, 240
; CHECK-NEXT: vst $vr0, $a0, 0
; CHECK-NEXT: ret
entry:
Expand All @@ -26,10 +24,8 @@ define void @shufflevector_v8i16(ptr %res, ptr %a, ptr %b) nounwind {
; CHECK-LABEL: shufflevector_v8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vld $vr0, $a1, 0
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI1_0)
; CHECK-NEXT: vld $vr1, $a1, %pc_lo12(.LCPI1_0)
; CHECK-NEXT: vshuf.h $vr1, $vr0, $vr0
; CHECK-NEXT: vst $vr1, $a0, 0
; CHECK-NEXT: vextrins.h $vr0, $vr0, 53
; CHECK-NEXT: vst $vr0, $a0, 0
; CHECK-NEXT: ret
entry:
%va = load <8 x i16>, ptr %a
Expand All @@ -41,15 +37,21 @@ entry:

;; vextrins.w
define void @shufflevector_v4i32(ptr %res, ptr %a, ptr %b) nounwind {
; CHECK-LABEL: shufflevector_v4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vld $vr0, $a1, 0
; CHECK-NEXT: vld $vr1, $a2, 0
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI2_0)
; CHECK-NEXT: vld $vr2, $a1, %pc_lo12(.LCPI2_0)
; CHECK-NEXT: vshuf.w $vr2, $vr1, $vr0
; CHECK-NEXT: vst $vr2, $a0, 0
; CHECK-NEXT: ret
; LA32-LABEL: shufflevector_v4i32:
; LA32: # %bb.0: # %entry
; LA32-NEXT: vld $vr0, $a2, 0
; LA32-NEXT: ld.w $a1, $a1, 12
; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 0
; LA32-NEXT: vst $vr0, $a0, 0
; LA32-NEXT: ret
;
; LA64-LABEL: shufflevector_v4i32:
; LA64: # %bb.0: # %entry
; LA64-NEXT: vld $vr0, $a1, 0
; LA64-NEXT: vld $vr1, $a2, 0
; LA64-NEXT: vextrins.w $vr1, $vr0, 3
; LA64-NEXT: vst $vr1, $a0, 0
; LA64-NEXT: ret
entry:
%va = load <4 x i32>, ptr %a
%vb = load <4 x i32>, ptr %b
Expand All @@ -62,12 +64,10 @@ entry:
define void @shufflevector_v4f32(ptr %res, ptr %a, ptr %b) nounwind {
; CHECK-LABEL: shufflevector_v4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vld $vr0, $a1, 0
; CHECK-NEXT: vld $vr1, $a2, 0
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI3_0)
; CHECK-NEXT: vld $vr2, $a1, %pc_lo12(.LCPI3_0)
; CHECK-NEXT: vshuf.w $vr2, $vr1, $vr0
; CHECK-NEXT: vst $vr2, $a0, 0
; CHECK-NEXT: vld $vr0, $a2, 0
; CHECK-NEXT: fld.s $fa1, $a1, 8
; CHECK-NEXT: vextrins.w $vr0, $vr1, 48
; CHECK-NEXT: vst $vr0, $a0, 0
; CHECK-NEXT: ret
entry:
%va = load <4 x float>, ptr %a
Expand Down
51 changes: 24 additions & 27 deletions llvm/test/CodeGen/LoongArch/lsx/vec-sext.ll
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Expand Up @@ -7,9 +7,7 @@ define void @load_sext_2i8_to_2i64(ptr %ptr, ptr %dst) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ld.h $a0, $a0, 0
; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
; CHECK-NEXT: vilvl.b $vr0, $vr0, $vr0
; CHECK-NEXT: vilvl.h $vr0, $vr0, $vr0
; CHECK-NEXT: vilvl.w $vr0, $vr0, $vr0
; CHECK-NEXT: vextrins.b $vr0, $vr0, 129
; CHECK-NEXT: vslli.d $vr0, $vr0, 56
; CHECK-NEXT: vsrai.d $vr0, $vr0, 56
; CHECK-NEXT: vst $vr0, $a1, 0
Expand Down Expand Up @@ -73,8 +71,7 @@ define void @load_sext_2i16_to_2i64(ptr %ptr, ptr %dst) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ld.w $a0, $a0, 0
; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
; CHECK-NEXT: vilvl.h $vr0, $vr0, $vr0
; CHECK-NEXT: vilvl.w $vr0, $vr0, $vr0
; CHECK-NEXT: vextrins.h $vr0, $vr0, 65
; CHECK-NEXT: vslli.d $vr0, $vr0, 48
; CHECK-NEXT: vsrai.d $vr0, $vr0, 48
; CHECK-NEXT: vst $vr0, $a1, 0
Expand Down Expand Up @@ -199,42 +196,42 @@ define void @load_sext_16i8_to_16i64(ptr %ptr, ptr %dst) {
; CHECK-NEXT: vld $vr0, $a0, 0
; CHECK-NEXT: vilvl.b $vr1, $vr0, $vr0
; CHECK-NEXT: vilvl.h $vr2, $vr1, $vr1
; CHECK-NEXT: vilvl.w $vr3, $vr2, $vr2
; CHECK-NEXT: vslli.d $vr3, $vr3, 56
; CHECK-NEXT: vsrai.d $vr3, $vr3, 56
; CHECK-NEXT: vilvh.w $vr2, $vr2, $vr2
; CHECK-NEXT: vslli.d $vr2, $vr2, 56
; CHECK-NEXT: vsrai.d $vr2, $vr2, 56
; CHECK-NEXT: vilvh.h $vr1, $vr1, $vr1
; CHECK-NEXT: vilvl.w $vr4, $vr1, $vr1
; CHECK-NEXT: vslli.d $vr4, $vr4, 56
; CHECK-NEXT: vsrai.d $vr4, $vr4, 56
; CHECK-NEXT: vilvl.w $vr3, $vr1, $vr1
; CHECK-NEXT: vslli.d $vr3, $vr3, 56
; CHECK-NEXT: vsrai.d $vr3, $vr3, 56
; CHECK-NEXT: vilvh.w $vr1, $vr1, $vr1
; CHECK-NEXT: vslli.d $vr1, $vr1, 56
; CHECK-NEXT: vsrai.d $vr1, $vr1, 56
; CHECK-NEXT: vilvh.b $vr0, $vr0, $vr0
; CHECK-NEXT: vilvl.h $vr5, $vr0, $vr0
; CHECK-NEXT: vilvh.b $vr4, $vr0, $vr0
; CHECK-NEXT: vilvl.h $vr5, $vr4, $vr4
; CHECK-NEXT: vilvl.w $vr6, $vr5, $vr5
; CHECK-NEXT: vslli.d $vr6, $vr6, 56
; CHECK-NEXT: vsrai.d $vr6, $vr6, 56
; CHECK-NEXT: vilvh.w $vr5, $vr5, $vr5
; CHECK-NEXT: vslli.d $vr5, $vr5, 56
; CHECK-NEXT: vsrai.d $vr5, $vr5, 56
; CHECK-NEXT: vilvh.h $vr0, $vr0, $vr0
; CHECK-NEXT: vilvl.w $vr7, $vr0, $vr0
; CHECK-NEXT: vilvh.h $vr4, $vr4, $vr4
; CHECK-NEXT: vilvl.w $vr7, $vr4, $vr4
; CHECK-NEXT: vslli.d $vr7, $vr7, 56
; CHECK-NEXT: vsrai.d $vr7, $vr7, 56
; CHECK-NEXT: vilvh.w $vr0, $vr0, $vr0
; CHECK-NEXT: vilvh.w $vr4, $vr4, $vr4
; CHECK-NEXT: vslli.d $vr4, $vr4, 56
; CHECK-NEXT: vsrai.d $vr4, $vr4, 56
; CHECK-NEXT: vextrins.b $vr0, $vr0, 129
; CHECK-NEXT: vslli.d $vr0, $vr0, 56
; CHECK-NEXT: vsrai.d $vr0, $vr0, 56
; CHECK-NEXT: vst $vr0, $a1, 112
; CHECK-NEXT: vst $vr0, $a1, 0
; CHECK-NEXT: vst $vr4, $a1, 112
; CHECK-NEXT: vst $vr7, $a1, 96
; CHECK-NEXT: vst $vr5, $a1, 80
; CHECK-NEXT: vst $vr6, $a1, 64
; CHECK-NEXT: vst $vr1, $a1, 48
; CHECK-NEXT: vst $vr4, $a1, 32
; CHECK-NEXT: vst $vr3, $a1, 32
; CHECK-NEXT: vst $vr2, $a1, 16
; CHECK-NEXT: vst $vr3, $a1, 0
; CHECK-NEXT: ret
entry:
%A = load <16 x i8>, ptr %ptr
Expand Down Expand Up @@ -268,23 +265,23 @@ define void @load_sext_8i16_to_8i64(ptr %ptr, ptr %dst) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vld $vr0, $a0, 0
; CHECK-NEXT: vilvl.h $vr1, $vr0, $vr0
; CHECK-NEXT: vilvl.w $vr2, $vr1, $vr1
; CHECK-NEXT: vslli.d $vr2, $vr2, 48
; CHECK-NEXT: vsrai.d $vr2, $vr2, 48
; CHECK-NEXT: vilvh.w $vr1, $vr1, $vr1
; CHECK-NEXT: vslli.d $vr1, $vr1, 48
; CHECK-NEXT: vsrai.d $vr1, $vr1, 48
; CHECK-NEXT: vilvh.h $vr0, $vr0, $vr0
; CHECK-NEXT: vilvl.w $vr3, $vr0, $vr0
; CHECK-NEXT: vilvh.h $vr2, $vr0, $vr0
; CHECK-NEXT: vilvl.w $vr3, $vr2, $vr2
; CHECK-NEXT: vslli.d $vr3, $vr3, 48
; CHECK-NEXT: vsrai.d $vr3, $vr3, 48
; CHECK-NEXT: vilvh.w $vr0, $vr0, $vr0
; CHECK-NEXT: vilvh.w $vr2, $vr2, $vr2
; CHECK-NEXT: vslli.d $vr2, $vr2, 48
; CHECK-NEXT: vsrai.d $vr2, $vr2, 48
; CHECK-NEXT: vextrins.h $vr0, $vr0, 65
; CHECK-NEXT: vslli.d $vr0, $vr0, 48
; CHECK-NEXT: vsrai.d $vr0, $vr0, 48
; CHECK-NEXT: vst $vr0, $a1, 48
; CHECK-NEXT: vst $vr0, $a1, 0
; CHECK-NEXT: vst $vr2, $a1, 48
; CHECK-NEXT: vst $vr3, $a1, 32
; CHECK-NEXT: vst $vr1, $a1, 16
; CHECK-NEXT: vst $vr2, $a1, 0
; CHECK-NEXT: ret
entry:
%A = load <8 x i16>, ptr %ptr
Expand Down
39 changes: 18 additions & 21 deletions llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-any-ext.ll
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Expand Up @@ -7,9 +7,7 @@ define void @shuffle_any_ext_2i8_to_2i64(ptr %ptr, ptr %dst) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: ld.h $a0, $a0, 0
; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
; CHECK-NEXT: vilvl.b $vr0, $vr0, $vr0
; CHECK-NEXT: vilvl.h $vr0, $vr0, $vr0
; CHECK-NEXT: vilvl.w $vr0, $vr0, $vr0
; CHECK-NEXT: vextrins.b $vr0, $vr0, 129
; CHECK-NEXT: vst $vr0, $a1, 0
; CHECK-NEXT: ret
%x = load <2 x i8>, ptr %ptr
Expand All @@ -24,8 +22,7 @@ define void @shuffle_any_ext_2i16_to_2i64(ptr %ptr, ptr %dst) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: ld.w $a0, $a0, 0
; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
; CHECK-NEXT: vilvl.h $vr0, $vr0, $vr0
; CHECK-NEXT: vilvl.w $vr0, $vr0, $vr0
; CHECK-NEXT: vextrins.h $vr0, $vr0, 65
; CHECK-NEXT: vst $vr0, $a1, 0
; CHECK-NEXT: ret
%x = load <2 x i16>, ptr %ptr
Expand Down Expand Up @@ -162,15 +159,15 @@ define void @shuffle_any_ext_8i16_to_8i64(ptr %ptr, ptr %dst) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: vld $vr0, $a0, 0
; CHECK-NEXT: vilvl.h $vr1, $vr0, $vr0
; CHECK-NEXT: vilvl.w $vr2, $vr1, $vr1
; CHECK-NEXT: vilvh.w $vr1, $vr1, $vr1
; CHECK-NEXT: vilvh.h $vr0, $vr0, $vr0
; CHECK-NEXT: vilvl.w $vr3, $vr0, $vr0
; CHECK-NEXT: vilvh.w $vr0, $vr0, $vr0
; CHECK-NEXT: vst $vr0, $a1, 48
; CHECK-NEXT: vilvh.h $vr2, $vr0, $vr0
; CHECK-NEXT: vilvl.w $vr3, $vr2, $vr2
; CHECK-NEXT: vilvh.w $vr2, $vr2, $vr2
; CHECK-NEXT: vextrins.h $vr0, $vr0, 65
; CHECK-NEXT: vst $vr0, $a1, 0
; CHECK-NEXT: vst $vr2, $a1, 48
; CHECK-NEXT: vst $vr3, $a1, 32
; CHECK-NEXT: vst $vr1, $a1, 16
; CHECK-NEXT: vst $vr2, $a1, 0
; CHECK-NEXT: ret
%x = load <8 x i16>, ptr %ptr
%y = shufflevector <8 x i16> %x, <8 x i16> poison, <32 x i32> <i32 0, i32 15, i32 15, i32 15, i32 1, i32 14, i32 14, i32 14, i32 2, i32 13, i32 13, i32 13, i32 3, i32 12, i32 12, i32 12, i32 4, i32 11, i32 11, i32 11, i32 5, i32 10, i32 10, i32 10, i32 6, i32 9, i32 9, i32 9, i32 7, i32 8, i32 8, i32 8>
Expand Down Expand Up @@ -223,26 +220,26 @@ define void @shuffle_any_ext_16i8_to_16i64(ptr %ptr, ptr %dst) nounwind {
; CHECK-NEXT: vld $vr0, $a0, 0
; CHECK-NEXT: vilvl.b $vr1, $vr0, $vr0
; CHECK-NEXT: vilvl.h $vr2, $vr1, $vr1
; CHECK-NEXT: vilvl.w $vr3, $vr2, $vr2
; CHECK-NEXT: vilvh.w $vr2, $vr2, $vr2
; CHECK-NEXT: vilvh.h $vr1, $vr1, $vr1
; CHECK-NEXT: vilvl.w $vr4, $vr1, $vr1
; CHECK-NEXT: vilvl.w $vr3, $vr1, $vr1
; CHECK-NEXT: vilvh.w $vr1, $vr1, $vr1
; CHECK-NEXT: vilvh.b $vr0, $vr0, $vr0
; CHECK-NEXT: vilvl.h $vr5, $vr0, $vr0
; CHECK-NEXT: vilvh.b $vr4, $vr0, $vr0
; CHECK-NEXT: vilvl.h $vr5, $vr4, $vr4
; CHECK-NEXT: vilvl.w $vr6, $vr5, $vr5
; CHECK-NEXT: vilvh.w $vr5, $vr5, $vr5
; CHECK-NEXT: vilvh.h $vr0, $vr0, $vr0
; CHECK-NEXT: vilvl.w $vr7, $vr0, $vr0
; CHECK-NEXT: vilvh.w $vr0, $vr0, $vr0
; CHECK-NEXT: vst $vr0, $a1, 112
; CHECK-NEXT: vilvh.h $vr4, $vr4, $vr4
; CHECK-NEXT: vilvl.w $vr7, $vr4, $vr4
; CHECK-NEXT: vilvh.w $vr4, $vr4, $vr4
; CHECK-NEXT: vextrins.b $vr0, $vr0, 129
; CHECK-NEXT: vst $vr0, $a1, 0
; CHECK-NEXT: vst $vr4, $a1, 112
; CHECK-NEXT: vst $vr7, $a1, 96
; CHECK-NEXT: vst $vr5, $a1, 80
; CHECK-NEXT: vst $vr6, $a1, 64
; CHECK-NEXT: vst $vr1, $a1, 48
; CHECK-NEXT: vst $vr4, $a1, 32
; CHECK-NEXT: vst $vr3, $a1, 32
; CHECK-NEXT: vst $vr2, $a1, 16
; CHECK-NEXT: vst $vr3, $a1, 0
; CHECK-NEXT: ret
%x = load <16 x i8>, ptr %ptr
%y = shufflevector <16 x i8> %x, <16 x i8> poison, <128 x i32> <i32 0, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 1, i32 30, i32 30, i32 30, i32 30, i32 30, i32 30, i32 30, i32 2, i32 29, i32 29, i32 29, i32 29, i32 29, i32 29, i32 29, i32 3, i32 28, i32 28, i32 28, i32 28, i32 28, i32 28, i32 28, i32 4, i32 27, i32 27, i32 27, i32 27, i32 27, i32 27, i32 27, i32 5, i32 26, i32 26, i32 26, i32 26, i32 26, i32 26, i32 26, i32 6, i32 25, i32 25, i32 25, i32 25, i32 25, i32 25, i32 25, i32 7, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 8, i32 23, i32 23, i32 23, i32 23, i32 23, i32 23, i32 23, i32 9, i32 22, i32 22, i32 22, i32 22, i32 22, i32 22, i32 22, i32 10, i32 21, i32 21, i32 21, i32 21, i32 21, i32 21, i32 21, i32 11, i32 20, i32 20, i32 20, i32 20, i32 20, i32 20, i32 20, i32 12, i32 19, i32 19, i32 19, i32 19, i32 19, i32 19, i32 19, i32 13, i32 18, i32 18, i32 18, i32 18, i32 18, i32 18, i32 18, i32 14, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
Expand Down
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