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[LoongArch] Type legalize v2f32 loads by using an f64 load and a scalar_to_vector #164943

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[LoongArch] Type legalize v2f32 loads by using an f64 load and a scalar_to_vector #164943

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28 changes: 28 additions & 0 deletions llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -386,6 +386,8 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::VECREDUCE_UMAX, VT, Custom);
setOperationAction(ISD::VECREDUCE_UMIN, VT, Custom);
}
// We want to legalize this to an f64 load rather than an i64 load.
setOperationAction(ISD::LOAD, MVT::v2f32, Custom);
}

// Set operations for 'LASX' feature.
Expand Down Expand Up @@ -4668,6 +4670,32 @@ void LoongArchTargetLowering::ReplaceNodeResults(
"Unexpected custom legalisation");
Results.push_back(customLegalizeToWOp(N, DAG, 2));
break;
case ISD::LOAD: {
// Use an f64 load and a scalar_to_vector for v2f32 loads. This avoids
// scalarizing in 32-bit mode. In 64-bit mode this avoids a int->fp
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Is there any tests for 32-bit?

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Thanks, I will add some tests.

// cast since type legalization will try to use an i64 load.
MVT VT = N->getSimpleValueType(0);
assert(VT == MVT::v2f32 && "Unexpected VT");
assert(getTypeAction(*DAG.getContext(), VT) == TypeWidenVector &&
"Unexpected type action!");
if (!ISD::isNON_EXTLoad(N))
return;
auto *Ld = cast<LoadSDNode>(N);
if (Subtarget.hasExtLSX()) {
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This maybe unnecessary?

MVT LdVT = MVT::f64;
SDValue Res = DAG.getLoad(LdVT, DL, Ld->getChain(), Ld->getBasePtr(),
Ld->getPointerInfo(), Ld->getBaseAlign(),
Ld->getMemOperand()->getFlags());
SDValue Chain = Res.getValue(1);
MVT VecVT = MVT::getVectorVT(LdVT, 2);
Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Res);
EVT WideVT = getTypeToTransformTo(*DAG.getContext(), VT);
Res = DAG.getBitcast(WideVT, Res);
Results.push_back(Res);
Results.push_back(Chain);
}
break;
}
case ISD::FP_TO_SINT: {
assert(VT == MVT::i32 && Subtarget.is64Bit() &&
"Unexpected custom legalisation");
Expand Down
3 changes: 1 addition & 2 deletions llvm/test/CodeGen/LoongArch/vector-fp-imm.ll
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Expand Up @@ -123,8 +123,7 @@ define void @test_f2(ptr %P, ptr %S) nounwind {
;
; LA64D-LABEL: test_f2:
; LA64D: # %bb.0:
; LA64D-NEXT: ld.d $a0, $a0, 0
; LA64D-NEXT: vinsgr2vr.d $vr0, $a0, 0
; LA64D-NEXT: fld.d $fa0, $a0, 0
; LA64D-NEXT: lu12i.w $a0, 260096
; LA64D-NEXT: lu52i.d $a0, $a0, 1024
; LA64D-NEXT: vreplgr2vr.d $vr1, $a0
Expand Down