[libc][fenv] Refactor x86 fenv implementations to make it work for various fenv_t.

[lntue]

No description provided.

[llvmbot]

@llvm/pr-subscribers-libc

Author: None (lntue)

Changes

---

Patch is 65.96 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/165015.diff

9 Files Affected:

• (modified) libc/src/__support/CPP/bit.h (+30-6)
• (modified) libc/src/__support/FPUtil/FEnvImpl.h (+1-7)
• (modified) libc/src/__support/FPUtil/x86_64/FEnvImpl.h (+179-580)
• (added) libc/src/__support/FPUtil/x86_64/fenv_mxcsr_utils.h (+129)
• (added) libc/src/__support/FPUtil/x86_64/fenv_x86_common.h (+253)
• (added) libc/src/__support/FPUtil/x86_64/fenv_x87_only.h (+137)
• (added) libc/src/__support/FPUtil/x86_64/fenv_x87_utils.h (+194)
• (modified) libc/src/__support/macros/properties/compiler.h (+5)
• (modified) libc/test/UnitTest/FEnvSafeTest.cpp (+44-20)

diff --git a/libc/src/__support/CPP/bit.h b/libc/src/__support/CPP/bit.h
index f602a7447ec10..5b244aa2a4b03 100644
--- a/libc/src/__support/CPP/bit.h
+++ b/libc/src/__support/CPP/bit.h
@@ -26,6 +26,16 @@ namespace cpp {
 #define LLVM_LIBC_HAS_BUILTIN_MEMCPY_INLINE
 #endif
 
+template <unsigned N>
+LIBC_INLINE static void inline_copy(const char *from, char *to) {
+#if __has_builtin(__builtin_memcpy_inline)
+  __builtin_memcpy_inline(to, from, N);
+#else
+  for (unsigned i = 0; i < N; ++i)
+    to[i] = from[i];
+#endif // __has_builtin(__builtin_memcpy_inline)
+}
+
 // This implementation of bit_cast requires trivially-constructible To, to avoid
 // UB in the implementation.
 template <typename To, typename From>
@@ -43,16 +53,30 @@ bit_cast(const From &from) {
   To to{};
   char *dst = reinterpret_cast<char *>(&to);
   const char *src = reinterpret_cast<const char *>(&from);
-#if __has_builtin(__builtin_memcpy_inline)
-  __builtin_memcpy_inline(dst, src, sizeof(To));
-#else
-  for (unsigned i = 0; i < sizeof(To); ++i)
-    dst[i] = src[i];
-#endif // __has_builtin(__builtin_memcpy_inline)
+  inline_copy<sizeof(From)>(src, dst);
   return to;
 #endif // __has_builtin(__builtin_bit_cast)
 }
 
+// The following simple bit copy from a smaller type to maybe-larger type.
+template <typename To, typename From>
+LIBC_INLINE constexpr cpp::enable_if_t<
+    (sizeof(To) >= sizeof(From)) &&
+        cpp::is_trivially_constructible<To>::value &&
+        cpp::is_trivially_copyable<To>::value &&
+        cpp::is_trivially_copyable<From>::value,
+    void>
+bit_copy(const From &from, To &to) {
+  MSAN_UNPOISON(&from, sizeof(From));
+  if constexpr (sizeof(To) == sizeof(From)) {
+    to = bit_cast<To>(from);
+  } else {
+    char *dst = reinterpret_cast<char *>(&to);
+    const char *src = reinterpret_cast<const char *>(&from);
+    inline_copy<sizeof(From)>(src, dst);
+  }
+}
+
 template <typename T>
 [[nodiscard]] LIBC_INLINE constexpr cpp::enable_if_t<cpp::is_unsigned_v<T>,
                                                      bool>
diff --git a/libc/src/__support/FPUtil/FEnvImpl.h b/libc/src/__support/FPUtil/FEnvImpl.h
index ef3f60a5b3d7f..3ef2df5f0a352 100644
--- a/libc/src/__support/FPUtil/FEnvImpl.h
+++ b/libc/src/__support/FPUtil/FEnvImpl.h
@@ -31,8 +31,7 @@
 // the dummy implementations below. Once a proper x86_64 darwin fenv is set up,
 // the apple condition here should be removed.
 // TODO: fully support fenv for MSVC.
-#elif defined(LIBC_TARGET_ARCH_IS_X86) && !defined(__APPLE__) &&               \
-    !defined(LIBC_COMPILER_IS_MSVC)
+#elif defined(LIBC_TARGET_ARCH_IS_X86) && !defined(__APPLE__)
 #include "x86_64/FEnvImpl.h"
 #elif defined(LIBC_TARGET_ARCH_IS_ARM) && defined(__ARM_FP) &&                 \
     !defined(LIBC_COMPILER_IS_MSVC)
@@ -110,12 +109,7 @@ raise_except_if_required([[maybe_unused]] int excepts) {
   } else {
 #ifndef LIBC_MATH_HAS_NO_EXCEPT
     if (math_errhandling & MATH_ERREXCEPT)
-#ifdef LIBC_TARGET_ARCH_IS_X86_64
-      return raise_except</*SKIP_X87_FPU*/ true>(excepts);
-#else  // !LIBC_TARGET_ARCH_IS_X86
       return raise_except(excepts);
-#endif // LIBC_TARGET_ARCH_IS_X86
-
 #endif // LIBC_MATH_HAS_NO_EXCEPT
     return 0;
   }
diff --git a/libc/src/__support/FPUtil/x86_64/FEnvImpl.h b/libc/src/__support/FPUtil/x86_64/FEnvImpl.h
index 5da509796d849..4dfd784fa9734 100644
--- a/libc/src/__support/FPUtil/x86_64/FEnvImpl.h
+++ b/libc/src/__support/FPUtil/x86_64/FEnvImpl.h
@@ -9,642 +9,241 @@
 #ifndef LLVM_LIBC_SRC___SUPPORT_FPUTIL_X86_64_FENVIMPL_H
 #define LLVM_LIBC_SRC___SUPPORT_FPUTIL_X86_64_FENVIMPL_H
 
+#include "hdr/fenv_macros.h"
+#include "hdr/stdint_proxy.h"
+#include "hdr/types/fenv_t.h"
+#include "src/__support/CPP/bit.h"
 #include "src/__support/macros/attributes.h" // LIBC_INLINE
 #include "src/__support/macros/config.h"
+#include "src/__support/macros/optimization.h"
 #include "src/__support/macros/properties/architectures.h"
+#include "src/__support/macros/properties/compiler.h"
+#include "src/__support/macros/properties/types.h"
 
 #if !defined(LIBC_TARGET_ARCH_IS_X86)
 #error "Invalid include"
 #endif
 
-#include "hdr/stdint_proxy.h"
-#include "hdr/types/fenv_t.h"
-#include "src/__support/macros/sanitizer.h"
+#ifndef __SSE__
+// When SSE is not available, we will only touch x87 floating point environment.
+#include "src/__support/FPUtil/x86_64/fenv_x87_only.h"
+#else // __SSE__
 
-namespace LIBC_NAMESPACE_DECL {
-namespace fputil {
+#ifndef LIBC_COMPILER_IS_MSVC
+#include "src/__support/FPUtil/x86_64/fenv_x87_utils.h"
+#endif // !LIBC_COMPILER_IS_MSVC
 
-namespace internal {
-
-// Normally, one should be able to define FE_* macros to the exact rounding mode
-// encodings. However, since we want LLVM libc to be compiled against headers
-// from other libcs, we cannot assume that FE_* macros are always defined in
-// such a manner. So, we will define enums corresponding to the x86_64 bit
-// encodings. The implementations can map from FE_* to the corresponding enum
-// values.
-
-// The rounding control values in the x87 control register and the MXCSR
-// register have the same 2-bit enoding but have different bit positions.
-// See below for the bit positions.
-struct RoundingControlValue {
-  static constexpr uint16_t TO_NEAREST = 0x0;
-  static constexpr uint16_t DOWNWARD = 0x1;
-  static constexpr uint16_t UPWARD = 0x2;
-  static constexpr uint16_t TOWARD_ZERO = 0x3;
-};
-
-static constexpr uint16_t X87_ROUNDING_CONTROL_BIT_POSITION = 10;
-static constexpr uint16_t MXCSR_ROUNDING_CONTROL_BIT_POSITION = 13;
-
-// The exception flags in the x87 status register and the MXCSR have the same
-// encoding as well as the same bit positions.
-struct ExceptionFlags {
-  static constexpr uint16_t INVALID_F = 0x1;
-  // Some libcs define __FE_DENORM corresponding to the denormal input
-  // exception and include it in FE_ALL_EXCEPTS. We define and use it to
-  // support compiling against headers provided by such libcs.
-  static constexpr uint16_t DENORMAL_F = 0x2;
-  static constexpr uint16_t DIV_BY_ZERO_F = 0x4;
-  static constexpr uint16_t OVERFLOW_F = 0x8;
-  static constexpr uint16_t UNDERFLOW_F = 0x10;
-  static constexpr uint16_t INEXACT_F = 0x20;
-};
-
-// The exception control bits occupy six bits, one bit for each exception.
-// In the x87 control word, they occupy the first 6 bits. In the MXCSR
-// register, they occupy bits 7 to 12.
-static constexpr uint16_t X87_EXCEPTION_CONTROL_BIT_POSITION = 0;
-static constexpr uint16_t X87_EXCEPTION_CONTROL_BIT_POSITION_HIGH = 24;
-static constexpr uint16_t MXCSR_EXCEPTION_CONTOL_BIT_POISTION = 7;
-
-// Exception flags are individual bits in the corresponding registers.
-// So, we just OR the bit values to get the full set of exceptions.
-LIBC_INLINE uint16_t get_status_value_for_except(int excepts) {
-  // We will make use of the fact that exception control bits are single
-  // bit flags in the control registers.
-  return ((excepts & FE_INVALID) ? ExceptionFlags::INVALID_F : 0) |
-#ifdef __FE_DENORM
-         ((excepts & __FE_DENORM) ? ExceptionFlags::DENORMAL_F : 0) |
-#endif // __FE_DENORM
-         ((excepts & FE_DIVBYZERO) ? ExceptionFlags::DIV_BY_ZERO_F : 0) |
-         ((excepts & FE_OVERFLOW) ? ExceptionFlags::OVERFLOW_F : 0) |
-         ((excepts & FE_UNDERFLOW) ? ExceptionFlags::UNDERFLOW_F : 0) |
-         ((excepts & FE_INEXACT) ? ExceptionFlags::INEXACT_F : 0);
-}
+#include "src/__support/FPUtil/x86_64/fenv_mxcsr_utils.h"
 
-LIBC_INLINE int exception_status_to_macro(uint16_t status) {
-  return ((status & ExceptionFlags::INVALID_F) ? FE_INVALID : 0) |
-#ifdef __FE_DENORM
-         ((status & ExceptionFlags::DENORMAL_F) ? __FE_DENORM : 0) |
-#endif // __FE_DENORM
-         ((status & ExceptionFlags::DIV_BY_ZERO_F) ? FE_DIVBYZERO : 0) |
-         ((status & ExceptionFlags::OVERFLOW_F) ? FE_OVERFLOW : 0) |
-         ((status & ExceptionFlags::UNDERFLOW_F) ? FE_UNDERFLOW : 0) |
-         ((status & ExceptionFlags::INEXACT_F) ? FE_INEXACT : 0);
-}
+namespace LIBC_NAMESPACE_DECL {
+namespace fputil {
 
-struct X87StateDescriptor {
-  uint16_t control_word;
-  uint16_t unused1;
-  uint16_t status_word;
-  uint16_t unused2;
-  // TODO: Elaborate the remaining 20 bytes as required.
-  uint32_t _[5];
-};
-
-LIBC_INLINE uint16_t get_x87_control_word() {
-  uint16_t w;
-  __asm__ __volatile__("fnstcw %0" : "=m"(w)::);
-  MSAN_UNPOISON(&w, sizeof(w));
-  return w;
-}
+LIBC_INLINE static int clear_except(int excepts) {
+  uint16_t x86_excepts = internal::get_status_value_from_except(excepts);
+  sse::clear_except(x86_excepts);
 
-LIBC_INLINE void write_x87_control_word(uint16_t w) {
-  __asm__ __volatile__("fldcw %0" : : "m"(w) :);
-}
+#ifdef LIBC_TYPES_LONG_DOUBLE_IS_X86_FLOAT80
+  x87::clear_except(x86_excepts);
+#endif // LIBC_TYPES_LONG_DOUBLE_IS_X86_FLOAT80
 
-LIBC_INLINE uint16_t get_x87_status_word() {
-  uint16_t w;
-  __asm__ __volatile__("fnstsw %0" : "=m"(w)::);
-  MSAN_UNPOISON(&w, sizeof(w));
-  return w;
-}
-
-LIBC_INLINE void clear_x87_exceptions() {
-  __asm__ __volatile__("fnclex" : : :);
-}
-
-LIBC_INLINE uint32_t get_mxcsr() {
-  uint32_t w;
-  __asm__ __volatile__("stmxcsr %0" : "=m"(w)::);
-  MSAN_UNPOISON(&w, sizeof(w));
-  return w;
+  return 0;
 }
 
-LIBC_INLINE void write_mxcsr(uint32_t w) {
-  __asm__ __volatile__("ldmxcsr %0" : : "m"(w) :);
-}
+LIBC_INLINE static int test_except(int excepts) {
+  uint16_t x86_excepts = internal::get_status_value_from_except(excepts);
+  uint16_t tested_excepts = sse::test_except(x86_excepts);
 
-LIBC_INLINE void get_x87_state_descriptor(X87StateDescriptor &s) {
-  __asm__ __volatile__("fnstenv %0" : "=m"(s));
-  MSAN_UNPOISON(&s, sizeof(s));
-}
+#ifdef LIBC_TYPES_LONG_DOUBLE_IS_X86_FLOAT80
+  tested_excepts |= x87::test_except(x86_excepts);
+#endif // LIBC_TYPES_LONG_DOUBLE_IS_X86_FLOAT80
 
-LIBC_INLINE void write_x87_state_descriptor(const X87StateDescriptor &s) {
-  __asm__ __volatile__("fldenv %0" : : "m"(s) :);
+  return internal::get_macro_from_exception_status(tested_excepts);
 }
 
-LIBC_INLINE void fwait() { __asm__ __volatile__("fwait"); }
-
-} // namespace internal
-
-LIBC_INLINE int enable_except(int excepts) {
-  // In the x87 control word and in MXCSR, an exception is blocked
-  // if the corresponding bit is set. That is the reason for all the
-  // bit-flip operations below as we need to turn the bits to zero
-  // to enable them.
-
-  uint16_t bit_mask = internal::get_status_value_for_except(excepts);
+LIBC_INLINE static int get_except() {
+  uint16_t excepts = sse::get_except();
 
-  uint16_t x87_cw = internal::get_x87_control_word();
-  uint16_t old_excepts = ~x87_cw & 0x3F; // Save previously enabled exceptions.
-  x87_cw &= ~bit_mask;
-  internal::write_x87_control_word(x87_cw);
+#ifdef LIBC_TYPES_LONG_DOUBLE_IS_X86_FLOAT80
+  excepts |= x87::get_except();
+#endif // LIBC_TYPES_LONG_DOUBLE_IS_X86_FLOAT80
 
-  // Enabling SSE exceptions via MXCSR is a nice thing to do but
-  // might not be of much use practically as SSE exceptions and the x87
-  // exceptions are independent of each other.
-  uint32_t mxcsr = internal::get_mxcsr();
-  mxcsr &= ~(bit_mask << internal::MXCSR_EXCEPTION_CONTOL_BIT_POISTION);
-  internal::write_mxcsr(mxcsr);
-
-  // Since the x87 exceptions and SSE exceptions are independent of each,
-  // it doesn't make much sence to report both in the return value. Most
-  // often, the standard floating point functions deal with FPU operations
-  // so we will retrun only the old x87 exceptions.
-  return internal::exception_status_to_macro(old_excepts);
+  return internal::get_macro_from_exception_status(excepts);
 }
 
-LIBC_INLINE int disable_except(int excepts) {
-  // In the x87 control word and in MXCSR, an exception is blocked
-  // if the corresponding bit is set.
-
-  uint16_t bit_mask = internal::get_status_value_for_except(excepts);
-
-  uint16_t x87_cw = internal::get_x87_control_word();
-  uint16_t old_excepts = ~x87_cw & 0x3F; // Save previously enabled exceptions.
-  x87_cw |= bit_mask;
-  internal::write_x87_control_word(x87_cw);
-
-  // Just like in enable_except, it is not clear if disabling SSE exceptions
-  // is required. But, we will still do it only as a "nice thing to do".
-  uint32_t mxcsr = internal::get_mxcsr();
-  mxcsr |= (bit_mask << internal::MXCSR_EXCEPTION_CONTOL_BIT_POISTION);
-  internal::write_mxcsr(mxcsr);
+LIBC_INLINE static int set_except(int excepts) {
+  uint16_t x86_excepts = internal::get_status_value_from_except(excepts);
+  sse::set_except(x86_excepts);
 
-  return internal::exception_status_to_macro(old_excepts);
-}
-
-LIBC_INLINE int get_except() {
-  uint16_t mxcsr = static_cast<uint16_t>(internal::get_mxcsr());
-  uint16_t enabled_excepts = ~(mxcsr >> 7) & 0x3F;
-  return internal::exception_status_to_macro(enabled_excepts);
-}
+#ifdef LIBC_TYPES_LONG_DOUBLE_IS_X86_FLOAT80
+  x87::set_except(x86_excepts);
+#endif // LIBC_TYPES_LONG_DOUBLE_IS_X86_FLOAT80
 
-LIBC_INLINE int clear_except(int excepts) {
-  internal::X87StateDescriptor state;
-  internal::get_x87_state_descriptor(state);
-  state.status_word &=
-      static_cast<uint16_t>(~internal::get_status_value_for_except(excepts));
-  internal::write_x87_state_descriptor(state);
-
-  uint32_t mxcsr = internal::get_mxcsr();
-  mxcsr &= ~internal::get_status_value_for_except(excepts);
-  internal::write_mxcsr(mxcsr);
   return 0;
 }
 
-LIBC_INLINE int test_except(int excepts) {
-  uint16_t status_word = internal::get_x87_status_word();
-  uint32_t mxcsr = internal::get_mxcsr();
-  // Check both x87 status word and MXCSR.
-  uint16_t status_value = internal::get_status_value_for_except(excepts);
-  return internal::exception_status_to_macro(
-      static_cast<uint16_t>(status_value & (status_word | mxcsr)));
-}
-
-// Sets the exception flags but does not trigger the exception handler.
-LIBC_INLINE int set_except(int excepts) {
-  uint16_t status_value = internal::get_status_value_for_except(excepts);
-  internal::X87StateDescriptor state;
-  internal::get_x87_state_descriptor(state);
-  state.status_word |= status_value;
-  internal::write_x87_state_descriptor(state);
-
-  uint32_t mxcsr = internal::get_mxcsr();
-  mxcsr |= status_value;
-  internal::write_mxcsr(mxcsr);
-
+// We will only OR sse exception flags.  Even though this might make x87 and
+// sse exception flags not in sync, the results will be synchronized when
+// reading with get_except or test_except.
+LIBC_INLINE static int raise_except(int excepts) {
+  uint16_t x86_excepts = internal::get_status_value_from_except(excepts);
+  sse::raise_except(x86_excepts);
   return 0;
 }
 
-template <bool SKIP_X87_FPU = false> LIBC_INLINE int raise_except(int excepts) {
-  uint16_t status_value = internal::get_status_value_for_except(excepts);
-
-  // We set the status flag for exception one at a time and call the
-  // fwait instruction to actually get the processor to raise the
-  // exception by calling the exception handler. This scheme is per
-  // the description in "8.6 X87 FPU EXCEPTION SYNCHRONIZATION"
-  // of the "Intel 64 and IA-32 Architectures Software Developer's
-  // Manual, Vol 1".
-
-  // FPU status word is read for each exception separately as the
-  // exception handler can potentially write to it (typically to clear
-  // the corresponding exception flag). By reading it separately, we
-  // ensure that the writes by the exception handler are maintained
-  // when raising the next exception.
-
-  auto raise_helper = [](uint16_t singleExceptFlag) {
-    if constexpr (!SKIP_X87_FPU) {
-      internal::X87StateDescriptor state;
-      internal::get_x87_state_descriptor(state);
-      state.status_word |= singleExceptFlag;
-      internal::write_x87_state_descriptor(state);
-    }
-
-    uint32_t mxcsr = 0;
-    mxcsr = internal::get_mxcsr();
-    mxcsr |= singleExceptFlag;
-    internal::write_mxcsr(mxcsr);
-    internal::fwait();
-  };
-
-  if (status_value & internal::ExceptionFlags::INVALID_F)
-    raise_helper(internal::ExceptionFlags::INVALID_F);
-  if (status_value & internal::ExceptionFlags::DIV_BY_ZERO_F)
-    raise_helper(internal::ExceptionFlags::DIV_BY_ZERO_F);
-  if (status_value & internal::ExceptionFlags::OVERFLOW_F)
-    raise_helper(internal::ExceptionFlags::OVERFLOW_F);
-  if (status_value & internal::ExceptionFlags::UNDERFLOW_F)
-    raise_helper(internal::ExceptionFlags::UNDERFLOW_F);
-  if (status_value & internal::ExceptionFlags::INEXACT_F)
-    raise_helper(internal::ExceptionFlags::INEXACT_F);
-#ifdef __FE_DENORM
-  if (status_value & internal::ExceptionFlags::DENORMAL_F) {
-    raise_helper(internal::ExceptionFlags::DENORMAL_F);
-  }
-#endif // __FE_DENORM
+LIBC_INLINE static int enable_except(int excepts) {
+  uint16_t x86_excepts = internal::get_status_value_from_except(excepts);
+  uint16_t old_excepts = sse::enable_except(x86_excepts);
 
-  // There is no special synchronization scheme available to
-  // raise SEE exceptions. So, we will ignore that for now.
-  // Just plain writing to the MXCSR register does not guarantee
-  // the exception handler will be called.
+#ifdef LIBC_TYPES_LONG_DOUBLE_IS_X86_FLOAT80
+  old_excepts |= x87::enable_except(x86_excepts);
+#endif // LIBC_TYPES_LONG_DOUBLE_IS_X86_FLOAT80
 
-  return 0;
+  return internal::get_macro_from_exception_status(old_excepts);
 }
 
-LIBC_INLINE int get_round() {
-  uint16_t bit_value =
-      (internal::get_mxcsr() >> internal::MXCSR_ROUNDING_CONTROL_BIT_POSITION) &
-      0x3;
-  switch (bit_value) {
-  case internal::RoundingControlValue::TO_NEAREST:
-    return FE_TONEAREST;
-  case internal::RoundingControlValue::DOWNWARD:
-    return FE_DOWNWARD;
-  case internal::RoundingControlValue::UPWARD:
-    return FE_UPWARD;
-  case internal::RoundingControlValue::TOWARD_ZERO:
-    return FE_TOWARDZERO;
-  default:
-    return -1; // Error value.
-  }
-}
-
-LIBC_INLINE int set_round(int mode) {
-  uint16_t bit_value;
-  switch (mode) {
-  case FE_TONEAREST:
-    bit_value = internal::RoundingControlValue::TO_NEAREST;
-    break;
-  case FE_DOWNWARD:
-    bit_value = internal::RoundingControlValue::DOWNWARD;
-    break;
-  case FE_UPWARD:
-    bit_value = internal::RoundingControlValue::UPWARD;
-    break;
-  case FE_TOWARDZERO:
-    bit_value = internal::RoundingControlValue::TOWARD_ZERO;
-    break;
-  default:
-    return 1; // To indicate failure
-  }
+LIBC_INLINE static int disable_except(int excepts) {
+  uint16_t x86_excepts = internal::get_status_value_from_except(excepts);
+  uint16_t old_excepts = sse::disable_except(x86_excepts);
 
-  uint16_t x87_value = static_cast<uint16_t>(
-      bit_value << internal::X87_ROUNDING_CONTROL_BIT_POSITION);
-  uint16_t x87_control = internal::get_x87_control_word();
-  x87_control = static_cast<uint16_t>(
-      (x87_control &
-       ~(uint16_t(0x3) << internal::X87_ROUNDING_CONTROL_BIT_POSITION)) |
-      x87_value);
-  internal::write_x87_control_word(x87_control);
-
-  uint32_t mxcsr_value = bit_value
-                         << internal::MXCSR_ROUNDING_CONTROL_BIT_POSITION;
-  uint32_t mxcsr_control = internal::get_mxcsr();
-  mxcsr_control = (mxcsr_control &
-                   ~(0x3 << internal::MXCSR_ROUNDING_CONTROL_BIT_POSITION)) |
-                  mxcsr_value;
-  internal::write_mxcsr(mxcsr_control);
+#ifdef LIBC_TYPES_LONG_DOUBLE_IS_X86_FLOAT80
+  old_excepts |= x87::disable_except(x86_excepts);
+#endif // LIBC_TYPES_LONG_DOUBLE_IS_X86_FLOAT80
 
-  return 0;
+  return internal::get_macro_from_exception_status(old_excepts);
 }
 
-namespace internal {
-
-#if defined(_WIN32)
-// MSVC fenv.h defines a very simple representation of the floating point state
-// which just consists of control and status words of the x87 unit.
-struct FPState {
-  uint32_t control_word;
-  uint32_t status_word;
-};
-#elif defined(__APPLE__)
-struct FPState {
-  uint16_t control_word;
-  uint16_t status_word;
-  uint32_t mxcsr;
-  uint8_t reserved[8];
-};
-#else
-struct FPState {
-  X87StateDescriptor x87_status;
-  uint32_t mxcsr;
-};
-#endif // _WIN32
-
-} // namespace internal
-
-static_assert(
-    sizeof(fenv_t) == sizeof(internal::FPState),
-    "Internal floating point state does not match the public fenv_t type.");
-
-#ifdef _WIN32
-
-// The exception flags in the Windows FEnv struct and the MXCSR have almost
-// reversed bit positions.
-struct WinExceptionFlags {
-  static constexpr uint32_t INEXACT_WIN = 0x01;
-  static constexpr uint32_t UNDERFLOW_WIN = 0x02;
-  static constexpr uint32_t OVERFLOW_WIN = 0x...
[truncated]

[github-actions]

✅ With the latest revision this PR passed the C/C++ code formatter.

[enh-google]

seems plausible, and -- though it's a lot of code compared to bionic's risc stuff -- it's not much worse than bionic's cisc stuff.