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[LoongArch] Add patterns for [X]VSTELM_W to adapt to LA32 #165224

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[LoongArch] Add patterns for [X]VSTELM_W to adapt to LA32 #165224

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5 changes: 4 additions & 1 deletion llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1920,10 +1920,13 @@ foreach vt = [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64] in
def : Pat<(vt (loongarch_xvreplve0q LASX256:$xj)),
(XVREPLVE0_Q LASX256:$xj)>;

// VSTELM
// XVSTELM
defm : VstelmPat<truncstorei8, v32i8, XVSTELM_B, simm8, uimm5>;
defm : VstelmPat<truncstorei16, v16i16, XVSTELM_H, simm8_lsl1, uimm4>;
defm : VstelmPat<truncstorei32, v8i32, XVSTELM_W, simm8_lsl2, uimm3>;
let Predicates = [IsLA32] in {
defm : VstelmPat<store, v8i32, XVSTELM_W, simm8_lsl2, uimm3>;
} // Predicates = [IsLA32]
defm : VstelmPat<store, v4i64, XVSTELM_D, simm8_lsl3, uimm2>;
defm : VstelmPat<store, v8f32, XVSTELM_W, simm8_lsl2, uimm3, f32>;
defm : VstelmPat<store, v4f64, XVSTELM_D, simm8_lsl3, uimm2, f64>;
Expand Down
4 changes: 4 additions & 0 deletions llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
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Expand Up @@ -2061,9 +2061,13 @@ def : Pat<(lsxsplatf32 FPR32:$fj),
def : Pat<(lsxsplatf64 FPR64:$fj),
(VREPLVEI_D (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64), 0)>;

// VSTELM
defm : VstelmPat<truncstorei8, v16i8, VSTELM_B, simm8, uimm4>;
defm : VstelmPat<truncstorei16, v8i16, VSTELM_H, simm8_lsl1, uimm3>;
defm : VstelmPat<truncstorei32, v4i32, VSTELM_W, simm8_lsl2, uimm2>;
let Predicates = [IsLA32] in {
defm : VstelmPat<store, v4i32, VSTELM_W, simm8_lsl2, uimm2>;
} // Predicates = [IsLA32]
defm : VstelmPat<store, v2i64, VSTELM_D, simm8_lsl3, uimm1>;
defm : VstelmPat<store, v4f32, VSTELM_W, simm8_lsl2, uimm2, f32>;
defm : VstelmPat<store, v2f64, VSTELM_D, simm8_lsl3, uimm1, f64>;
Expand Down
60 changes: 20 additions & 40 deletions llvm/test/CodeGen/LoongArch/lasx/ir-instruction/extractelement.ll
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Expand Up @@ -27,18 +27,11 @@ define void @extract_16xi16(ptr %src, ptr %dst) nounwind {
}

define void @extract_8xi32(ptr %src, ptr %dst) nounwind {
; LA32-LABEL: extract_8xi32:
; LA32: # %bb.0:
; LA32-NEXT: xvld $xr0, $a0, 0
; LA32-NEXT: xvpickve2gr.w $a0, $xr0, 1
; LA32-NEXT: st.w $a0, $a1, 0
; LA32-NEXT: ret
;
; LA64-LABEL: extract_8xi32:
; LA64: # %bb.0:
; LA64-NEXT: xvld $xr0, $a0, 0
; LA64-NEXT: xvstelm.w $xr0, $a1, 0, 1
; LA64-NEXT: ret
; CHECK-LABEL: extract_8xi32:
; CHECK: # %bb.0:
; CHECK-NEXT: xvld $xr0, $a0, 0
; CHECK-NEXT: xvstelm.w $xr0, $a1, 0, 1
; CHECK-NEXT: ret
%v = load volatile <8 x i32>, ptr %src
%e = extractelement <8 x i32> %v, i32 1
store i32 %e, ptr %dst
Expand All @@ -49,10 +42,8 @@ define void @extract_4xi64(ptr %src, ptr %dst) nounwind {
; LA32-LABEL: extract_4xi64:
; LA32: # %bb.0:
; LA32-NEXT: xvld $xr0, $a0, 0
; LA32-NEXT: xvpickve2gr.w $a0, $xr0, 2
; LA32-NEXT: xvpickve2gr.w $a2, $xr0, 3
; LA32-NEXT: st.w $a2, $a1, 4
; LA32-NEXT: st.w $a0, $a1, 0
; LA32-NEXT: xvstelm.w $xr0, $a1, 4, 3
; LA32-NEXT: xvstelm.w $xr0, $a1, 0, 2
; LA32-NEXT: ret
;
; LA64-LABEL: extract_4xi64:
Expand Down Expand Up @@ -139,22 +130,13 @@ define void @extract_16xi16_idx(ptr %src, ptr %dst, i32 %idx) nounwind {
}

define void @extract_8xi32_idx(ptr %src, ptr %dst, i32 %idx) nounwind {
; LA32-LABEL: extract_8xi32_idx:
; LA32: # %bb.0:
; LA32-NEXT: xvld $xr0, $a0, 0
; LA32-NEXT: xvreplgr2vr.w $xr1, $a2
; LA32-NEXT: xvperm.w $xr0, $xr0, $xr1
; LA32-NEXT: xvpickve2gr.w $a0, $xr0, 0
; LA32-NEXT: st.w $a0, $a1, 0
; LA32-NEXT: ret
;
; LA64-LABEL: extract_8xi32_idx:
; LA64: # %bb.0:
; LA64-NEXT: xvld $xr0, $a0, 0
; LA64-NEXT: xvreplgr2vr.w $xr1, $a2
; LA64-NEXT: xvperm.w $xr0, $xr0, $xr1
; LA64-NEXT: xvstelm.w $xr0, $a1, 0, 0
; LA64-NEXT: ret
; CHECK-LABEL: extract_8xi32_idx:
; CHECK: # %bb.0:
; CHECK-NEXT: xvld $xr0, $a0, 0
; CHECK-NEXT: xvreplgr2vr.w $xr1, $a2
; CHECK-NEXT: xvperm.w $xr0, $xr0, $xr1
; CHECK-NEXT: xvstelm.w $xr0, $a1, 0, 0
; CHECK-NEXT: ret
%v = load volatile <8 x i32>, ptr %src
%e = extractelement <8 x i32> %v, i32 %idx
store i32 %e, ptr %dst
Expand All @@ -169,12 +151,10 @@ define void @extract_4xi64_idx(ptr %src, ptr %dst, i32 %idx) nounwind {
; LA32-NEXT: addi.w $a2, $a0, 1
; LA32-NEXT: xvreplgr2vr.w $xr1, $a2
; LA32-NEXT: xvperm.w $xr1, $xr0, $xr1
; LA32-NEXT: xvpickve2gr.w $a2, $xr1, 0
; LA32-NEXT: xvreplgr2vr.w $xr1, $a0
; LA32-NEXT: xvperm.w $xr0, $xr0, $xr1
; LA32-NEXT: xvpickve2gr.w $a0, $xr0, 0
; LA32-NEXT: st.w $a0, $a1, 0
; LA32-NEXT: st.w $a2, $a1, 4
; LA32-NEXT: xvreplgr2vr.w $xr2, $a0
; LA32-NEXT: xvperm.w $xr0, $xr0, $xr2
; LA32-NEXT: xvstelm.w $xr0, $a1, 0, 0
; LA32-NEXT: xvstelm.w $xr1, $a1, 4, 0
; LA32-NEXT: ret
;
; LA64-LABEL: extract_4xi64_idx:
Expand Down Expand Up @@ -233,8 +213,8 @@ define void @eliminate_frame_index(<8 x i32> %a) nounwind {
; LA32-LABEL: eliminate_frame_index:
; LA32: # %bb.0:
; LA32-NEXT: addi.w $sp, $sp, -1040
; LA32-NEXT: xvpickve2gr.w $a0, $xr0, 1
; LA32-NEXT: st.w $a0, $sp, 524
; LA32-NEXT: addi.w $a0, $sp, 524
; LA32-NEXT: xvstelm.w $xr0, $a0, 0, 1
; LA32-NEXT: addi.w $sp, $sp, 1040
; LA32-NEXT: ret
;
Expand Down
3 changes: 1 addition & 2 deletions llvm/test/CodeGen/LoongArch/lasx/vec-reduce-add.ll
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Expand Up @@ -72,8 +72,7 @@ define void @vec_reduce_add_v8i32(ptr %src, ptr %dst) nounwind {
; LA32-NEXT: xvhaddw.q.d $xr0, $xr0, $xr0
; LA32-NEXT: xvpermi.d $xr1, $xr0, 2
; LA32-NEXT: xvadd.d $xr0, $xr1, $xr0
; LA32-NEXT: xvpickve2gr.w $a0, $xr0, 0
; LA32-NEXT: st.w $a0, $a1, 0
; LA32-NEXT: xvstelm.w $xr0, $a1, 0, 0
; LA32-NEXT: ret
;
; LA64-LABEL: vec_reduce_add_v8i32:
Expand Down
35 changes: 11 additions & 24 deletions llvm/test/CodeGen/LoongArch/lasx/vec-reduce-and.ll
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Expand Up @@ -45,30 +45,17 @@ define void @vec_reduce_and_v16i16(ptr %src, ptr %dst) nounwind {
}

define void @vec_reduce_and_v8i32(ptr %src, ptr %dst) nounwind {
; LA32-LABEL: vec_reduce_and_v8i32:
; LA32: # %bb.0:
; LA32-NEXT: xvld $xr0, $a0, 0
; LA32-NEXT: xvpermi.q $xr1, $xr0, 1
; LA32-NEXT: vand.v $vr0, $vr0, $vr1
; LA32-NEXT: vbsrl.v $vr1, $vr0, 8
; LA32-NEXT: vand.v $vr0, $vr1, $vr0
; LA32-NEXT: vbsrl.v $vr1, $vr0, 4
; LA32-NEXT: vand.v $vr0, $vr1, $vr0
; LA32-NEXT: vpickve2gr.w $a0, $vr0, 0
; LA32-NEXT: st.w $a0, $a1, 0
; LA32-NEXT: ret
;
; LA64-LABEL: vec_reduce_and_v8i32:
; LA64: # %bb.0:
; LA64-NEXT: xvld $xr0, $a0, 0
; LA64-NEXT: xvpermi.q $xr1, $xr0, 1
; LA64-NEXT: vand.v $vr0, $vr0, $vr1
; LA64-NEXT: vbsrl.v $vr1, $vr0, 8
; LA64-NEXT: vand.v $vr0, $vr1, $vr0
; LA64-NEXT: vbsrl.v $vr1, $vr0, 4
; LA64-NEXT: vand.v $vr0, $vr1, $vr0
; LA64-NEXT: vstelm.w $vr0, $a1, 0, 0
; LA64-NEXT: ret
; CHECK-LABEL: vec_reduce_and_v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: xvld $xr0, $a0, 0
; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1
; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8
; CHECK-NEXT: vand.v $vr0, $vr1, $vr0
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4
; CHECK-NEXT: vand.v $vr0, $vr1, $vr0
; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0
; CHECK-NEXT: ret
%v = load <8 x i32>, ptr %src
%res = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> %v)
store i32 %res, ptr %dst
Expand Down
35 changes: 11 additions & 24 deletions llvm/test/CodeGen/LoongArch/lasx/vec-reduce-or.ll
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Expand Up @@ -45,30 +45,17 @@ define void @vec_reduce_or_v16i16(ptr %src, ptr %dst) nounwind {
}

define void @vec_reduce_or_v8i32(ptr %src, ptr %dst) nounwind {
; LA32-LABEL: vec_reduce_or_v8i32:
; LA32: # %bb.0:
; LA32-NEXT: xvld $xr0, $a0, 0
; LA32-NEXT: xvpermi.q $xr1, $xr0, 1
; LA32-NEXT: vor.v $vr0, $vr0, $vr1
; LA32-NEXT: vbsrl.v $vr1, $vr0, 8
; LA32-NEXT: vor.v $vr0, $vr1, $vr0
; LA32-NEXT: vbsrl.v $vr1, $vr0, 4
; LA32-NEXT: vor.v $vr0, $vr1, $vr0
; LA32-NEXT: vpickve2gr.w $a0, $vr0, 0
; LA32-NEXT: st.w $a0, $a1, 0
; LA32-NEXT: ret
;
; LA64-LABEL: vec_reduce_or_v8i32:
; LA64: # %bb.0:
; LA64-NEXT: xvld $xr0, $a0, 0
; LA64-NEXT: xvpermi.q $xr1, $xr0, 1
; LA64-NEXT: vor.v $vr0, $vr0, $vr1
; LA64-NEXT: vbsrl.v $vr1, $vr0, 8
; LA64-NEXT: vor.v $vr0, $vr1, $vr0
; LA64-NEXT: vbsrl.v $vr1, $vr0, 4
; LA64-NEXT: vor.v $vr0, $vr1, $vr0
; LA64-NEXT: vstelm.w $vr0, $a1, 0, 0
; LA64-NEXT: ret
; CHECK-LABEL: vec_reduce_or_v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: xvld $xr0, $a0, 0
; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1
; CHECK-NEXT: vor.v $vr0, $vr0, $vr1
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8
; CHECK-NEXT: vor.v $vr0, $vr1, $vr0
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4
; CHECK-NEXT: vor.v $vr0, $vr1, $vr0
; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0
; CHECK-NEXT: ret
%v = load <8 x i32>, ptr %src
%res = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> %v)
store i32 %res, ptr %dst
Expand Down
35 changes: 11 additions & 24 deletions llvm/test/CodeGen/LoongArch/lasx/vec-reduce-smax.ll
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Expand Up @@ -45,30 +45,17 @@ define void @vec_reduce_smax_v16i16(ptr %src, ptr %dst) nounwind {
}

define void @vec_reduce_smax_v8i32(ptr %src, ptr %dst) nounwind {
; LA32-LABEL: vec_reduce_smax_v8i32:
; LA32: # %bb.0:
; LA32-NEXT: xvld $xr0, $a0, 0
; LA32-NEXT: xvpermi.q $xr1, $xr0, 1
; LA32-NEXT: vmax.w $vr0, $vr0, $vr1
; LA32-NEXT: vbsrl.v $vr1, $vr0, 8
; LA32-NEXT: vmax.w $vr0, $vr1, $vr0
; LA32-NEXT: vbsrl.v $vr1, $vr0, 4
; LA32-NEXT: vmax.w $vr0, $vr1, $vr0
; LA32-NEXT: vpickve2gr.w $a0, $vr0, 0
; LA32-NEXT: st.w $a0, $a1, 0
; LA32-NEXT: ret
;
; LA64-LABEL: vec_reduce_smax_v8i32:
; LA64: # %bb.0:
; LA64-NEXT: xvld $xr0, $a0, 0
; LA64-NEXT: xvpermi.q $xr1, $xr0, 1
; LA64-NEXT: vmax.w $vr0, $vr0, $vr1
; LA64-NEXT: vbsrl.v $vr1, $vr0, 8
; LA64-NEXT: vmax.w $vr0, $vr1, $vr0
; LA64-NEXT: vbsrl.v $vr1, $vr0, 4
; LA64-NEXT: vmax.w $vr0, $vr1, $vr0
; LA64-NEXT: vstelm.w $vr0, $a1, 0, 0
; LA64-NEXT: ret
; CHECK-LABEL: vec_reduce_smax_v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: xvld $xr0, $a0, 0
; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1
; CHECK-NEXT: vmax.w $vr0, $vr0, $vr1
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8
; CHECK-NEXT: vmax.w $vr0, $vr1, $vr0
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4
; CHECK-NEXT: vmax.w $vr0, $vr1, $vr0
; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0
; CHECK-NEXT: ret
%v = load <8 x i32>, ptr %src
%res = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> %v)
store i32 %res, ptr %dst
Expand Down
35 changes: 11 additions & 24 deletions llvm/test/CodeGen/LoongArch/lasx/vec-reduce-smin.ll
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Expand Up @@ -45,30 +45,17 @@ define void @vec_reduce_smin_v16i16(ptr %src, ptr %dst) nounwind {
}

define void @vec_reduce_smin_v8i32(ptr %src, ptr %dst) nounwind {
; LA32-LABEL: vec_reduce_smin_v8i32:
; LA32: # %bb.0:
; LA32-NEXT: xvld $xr0, $a0, 0
; LA32-NEXT: xvpermi.q $xr1, $xr0, 1
; LA32-NEXT: vmin.w $vr0, $vr0, $vr1
; LA32-NEXT: vbsrl.v $vr1, $vr0, 8
; LA32-NEXT: vmin.w $vr0, $vr1, $vr0
; LA32-NEXT: vbsrl.v $vr1, $vr0, 4
; LA32-NEXT: vmin.w $vr0, $vr1, $vr0
; LA32-NEXT: vpickve2gr.w $a0, $vr0, 0
; LA32-NEXT: st.w $a0, $a1, 0
; LA32-NEXT: ret
;
; LA64-LABEL: vec_reduce_smin_v8i32:
; LA64: # %bb.0:
; LA64-NEXT: xvld $xr0, $a0, 0
; LA64-NEXT: xvpermi.q $xr1, $xr0, 1
; LA64-NEXT: vmin.w $vr0, $vr0, $vr1
; LA64-NEXT: vbsrl.v $vr1, $vr0, 8
; LA64-NEXT: vmin.w $vr0, $vr1, $vr0
; LA64-NEXT: vbsrl.v $vr1, $vr0, 4
; LA64-NEXT: vmin.w $vr0, $vr1, $vr0
; LA64-NEXT: vstelm.w $vr0, $a1, 0, 0
; LA64-NEXT: ret
; CHECK-LABEL: vec_reduce_smin_v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: xvld $xr0, $a0, 0
; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1
; CHECK-NEXT: vmin.w $vr0, $vr0, $vr1
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8
; CHECK-NEXT: vmin.w $vr0, $vr1, $vr0
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4
; CHECK-NEXT: vmin.w $vr0, $vr1, $vr0
; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0
; CHECK-NEXT: ret
%v = load <8 x i32>, ptr %src
%res = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> %v)
store i32 %res, ptr %dst
Expand Down
35 changes: 11 additions & 24 deletions llvm/test/CodeGen/LoongArch/lasx/vec-reduce-umax.ll
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Expand Up @@ -45,30 +45,17 @@ define void @vec_reduce_umax_v16i16(ptr %src, ptr %dst) nounwind {
}

define void @vec_reduce_umax_v8i32(ptr %src, ptr %dst) nounwind {
; LA32-LABEL: vec_reduce_umax_v8i32:
; LA32: # %bb.0:
; LA32-NEXT: xvld $xr0, $a0, 0
; LA32-NEXT: xvpermi.q $xr1, $xr0, 1
; LA32-NEXT: vmax.wu $vr0, $vr0, $vr1
; LA32-NEXT: vbsrl.v $vr1, $vr0, 8
; LA32-NEXT: vmax.wu $vr0, $vr1, $vr0
; LA32-NEXT: vbsrl.v $vr1, $vr0, 4
; LA32-NEXT: vmax.wu $vr0, $vr1, $vr0
; LA32-NEXT: vpickve2gr.w $a0, $vr0, 0
; LA32-NEXT: st.w $a0, $a1, 0
; LA32-NEXT: ret
;
; LA64-LABEL: vec_reduce_umax_v8i32:
; LA64: # %bb.0:
; LA64-NEXT: xvld $xr0, $a0, 0
; LA64-NEXT: xvpermi.q $xr1, $xr0, 1
; LA64-NEXT: vmax.wu $vr0, $vr0, $vr1
; LA64-NEXT: vbsrl.v $vr1, $vr0, 8
; LA64-NEXT: vmax.wu $vr0, $vr1, $vr0
; LA64-NEXT: vbsrl.v $vr1, $vr0, 4
; LA64-NEXT: vmax.wu $vr0, $vr1, $vr0
; LA64-NEXT: vstelm.w $vr0, $a1, 0, 0
; LA64-NEXT: ret
; CHECK-LABEL: vec_reduce_umax_v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: xvld $xr0, $a0, 0
; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1
; CHECK-NEXT: vmax.wu $vr0, $vr0, $vr1
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8
; CHECK-NEXT: vmax.wu $vr0, $vr1, $vr0
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4
; CHECK-NEXT: vmax.wu $vr0, $vr1, $vr0
; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0
; CHECK-NEXT: ret
%v = load <8 x i32>, ptr %src
%res = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> %v)
store i32 %res, ptr %dst
Expand Down
35 changes: 11 additions & 24 deletions llvm/test/CodeGen/LoongArch/lasx/vec-reduce-umin.ll
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Expand Up @@ -45,30 +45,17 @@ define void @vec_reduce_umin_v16i16(ptr %src, ptr %dst) nounwind {
}

define void @vec_reduce_umin_v8i32(ptr %src, ptr %dst) nounwind {
; LA32-LABEL: vec_reduce_umin_v8i32:
; LA32: # %bb.0:
; LA32-NEXT: xvld $xr0, $a0, 0
; LA32-NEXT: xvpermi.q $xr1, $xr0, 1
; LA32-NEXT: vmin.wu $vr0, $vr0, $vr1
; LA32-NEXT: vbsrl.v $vr1, $vr0, 8
; LA32-NEXT: vmin.wu $vr0, $vr1, $vr0
; LA32-NEXT: vbsrl.v $vr1, $vr0, 4
; LA32-NEXT: vmin.wu $vr0, $vr1, $vr0
; LA32-NEXT: vpickve2gr.w $a0, $vr0, 0
; LA32-NEXT: st.w $a0, $a1, 0
; LA32-NEXT: ret
;
; LA64-LABEL: vec_reduce_umin_v8i32:
; LA64: # %bb.0:
; LA64-NEXT: xvld $xr0, $a0, 0
; LA64-NEXT: xvpermi.q $xr1, $xr0, 1
; LA64-NEXT: vmin.wu $vr0, $vr0, $vr1
; LA64-NEXT: vbsrl.v $vr1, $vr0, 8
; LA64-NEXT: vmin.wu $vr0, $vr1, $vr0
; LA64-NEXT: vbsrl.v $vr1, $vr0, 4
; LA64-NEXT: vmin.wu $vr0, $vr1, $vr0
; LA64-NEXT: vstelm.w $vr0, $a1, 0, 0
; LA64-NEXT: ret
; CHECK-LABEL: vec_reduce_umin_v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: xvld $xr0, $a0, 0
; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1
; CHECK-NEXT: vmin.wu $vr0, $vr0, $vr1
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8
; CHECK-NEXT: vmin.wu $vr0, $vr1, $vr0
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4
; CHECK-NEXT: vmin.wu $vr0, $vr1, $vr0
; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0
; CHECK-NEXT: ret
%v = load <8 x i32>, ptr %src
%res = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> %v)
store i32 %res, ptr %dst
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