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[GlobalISel] Rename G_ABDS/G_ABDU to G_SABD/G_UABD #165236

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[GlobalISel] Rename G_ABDS/G_ABDU to G_SABD/G_UABD #165236

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6 changes: 3 additions & 3 deletions llvm/docs/GlobalISel/GenericOpcode.rst
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Expand Up @@ -501,15 +501,15 @@ undefined.
%2:_(s33) = G_CTLZ_ZERO_UNDEF %1
%2:_(s33) = G_CTTZ_ZERO_UNDEF %1

G_ABDS, G_ABDU
G_SABD, G_UABD
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

Compute the absolute difference (signed and unsigned), e.g. trunc(abs(ext(x)-ext(y)).

.. code-block:: none

%0:_(s33) = G_ABDS %2, %3
%1:_(s33) = G_ABDU %4, %5
%0:_(s33) = G_SABD %2, %3
%1:_(s33) = G_UABD %4, %5

Floating Point Operations
-------------------------
Expand Down
16 changes: 8 additions & 8 deletions llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
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Expand Up @@ -1884,32 +1884,32 @@ class LLVM_ABI MachineIRBuilder {
return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1}, Flags);
}

/// Build and insert \p Res = G_ABDS \p Op0, \p Op1
/// Build and insert \p Res = G_SABD \p Op0, \p Op1
///
/// G_ABDS return the signed absolute difference of \p Op0 and \p Op1.
/// G_SABD return the signed absolute difference of \p Op0 and \p Op1.
///
/// \pre setBasicBlock or setMI must have been called.
/// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
/// with the same (scalar or vector) type).
///
/// \return a MachineInstrBuilder for the newly created instruction.
MachineInstrBuilder buildAbds(const DstOp &Dst, const SrcOp &Src0,
MachineInstrBuilder buildSAbd(const DstOp &Dst, const SrcOp &Src0,
const SrcOp &Src1) {
return buildInstr(TargetOpcode::G_ABDS, {Dst}, {Src0, Src1});
return buildInstr(TargetOpcode::G_SABD, {Dst}, {Src0, Src1});
}

/// Build and insert \p Res = G_ABDU \p Op0, \p Op1
/// Build and insert \p Res = G_UABD \p Op0, \p Op1
///
/// G_ABDU return the unsigned absolute difference of \p Op0 and \p Op1.
/// G_UABD return the unsigned absolute difference of \p Op0 and \p Op1.
///
/// \pre setBasicBlock or setMI must have been called.
/// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
/// with the same (scalar or vector) type).
///
/// \return a MachineInstrBuilder for the newly created instruction.
MachineInstrBuilder buildAbdu(const DstOp &Dst, const SrcOp &Src0,
MachineInstrBuilder buildUAbd(const DstOp &Dst, const SrcOp &Src0,
const SrcOp &Src1) {
return buildInstr(TargetOpcode::G_ABDU, {Dst}, {Src0, Src1});
return buildInstr(TargetOpcode::G_UABD, {Dst}, {Src0, Src1});
}

MachineInstrBuilder buildUMulH(const DstOp &Dst, const SrcOp &Src0,
Expand Down
4 changes: 2 additions & 2 deletions llvm/include/llvm/Support/TargetOpcodes.def
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Expand Up @@ -290,10 +290,10 @@ HANDLE_TARGET_OPCODE(G_OR)
HANDLE_TARGET_OPCODE(G_XOR)

/// Generic absolute difference signed instruction.
HANDLE_TARGET_OPCODE(G_ABDS)
HANDLE_TARGET_OPCODE(G_SABD)

/// Generic absolute difference unsigned instruction.
HANDLE_TARGET_OPCODE(G_ABDU)
HANDLE_TARGET_OPCODE(G_UABD)


HANDLE_TARGET_OPCODE(G_IMPLICIT_DEF)
Expand Down
4 changes: 2 additions & 2 deletions llvm/include/llvm/Target/GenericOpcodes.td
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Expand Up @@ -408,15 +408,15 @@ def G_ASHR : GenericInstruction {
}

// Generic absolute difference signed.
def G_ABDS : GenericInstruction {
def G_SABD : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2);
let hasSideEffects = false;
let isCommutable = true;
}

// Generic absolute difference unsigned.
def G_ABDU : GenericInstruction {
def G_UABD : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2);
let hasSideEffects = false;
Expand Down
4 changes: 2 additions & 2 deletions llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
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Expand Up @@ -81,8 +81,8 @@ def : GINodeEquiv<G_XOR, xor>;
def : GINodeEquiv<G_SHL, shl>;
def : GINodeEquiv<G_LSHR, srl>;
def : GINodeEquiv<G_ASHR, sra>;
def : GINodeEquiv<G_ABDS, abds>;
def : GINodeEquiv<G_ABDU, abdu>;
def : GINodeEquiv<G_SABD, abds>;
def : GINodeEquiv<G_UABD, abdu>;
def : GINodeEquiv<G_SADDSAT, saddsat>;
def : GINodeEquiv<G_UADDSAT, uaddsat>;
def : GINodeEquiv<G_SSUBSAT, ssubsat>;
Expand Down
26 changes: 13 additions & 13 deletions llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
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Expand Up @@ -2974,7 +2974,7 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
case TargetOpcode::G_SREM:
case TargetOpcode::G_SMIN:
case TargetOpcode::G_SMAX:
case TargetOpcode::G_ABDS:
case TargetOpcode::G_SABD:
Observer.changingInstr(MI);
widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
Expand Down Expand Up @@ -3013,7 +3013,7 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
return Legalized;
case TargetOpcode::G_UDIV:
case TargetOpcode::G_UREM:
case TargetOpcode::G_ABDU:
case TargetOpcode::G_UABD:
Observer.changingInstr(MI);
widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
Expand Down Expand Up @@ -4819,9 +4819,9 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) {
return lowerShlSat(MI);
case G_ABS:
return lowerAbsToAddXor(MI);
case G_ABDS:
case G_ABDU: {
bool IsSigned = MI.getOpcode() == G_ABDS;
case G_SABD:
case G_UABD: {
bool IsSigned = MI.getOpcode() == G_SABD;
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
if ((IsSigned && LI.isLegal({G_SMIN, Ty}) && LI.isLegal({G_SMAX, Ty})) ||
(!IsSigned && LI.isLegal({G_UMIN, Ty}) && LI.isLegal({G_UMAX, Ty}))) {
Expand Down Expand Up @@ -10134,9 +10134,9 @@ LegalizerHelper::lowerAbsToCNeg(MachineInstr &MI) {

LegalizerHelper::LegalizeResult
LegalizerHelper::lowerAbsDiffToSelect(MachineInstr &MI) {
assert((MI.getOpcode() == TargetOpcode::G_ABDS ||
MI.getOpcode() == TargetOpcode::G_ABDU) &&
"Expected G_ABDS or G_ABDU instruction");
assert((MI.getOpcode() == TargetOpcode::G_SABD ||
MI.getOpcode() == TargetOpcode::G_UABD) &&
"Expected G_SABD or G_UABD instruction");

auto [DstReg, LHS, RHS] = MI.getFirst3Regs();
LLT Ty = MRI.getType(LHS);
Expand All @@ -10145,7 +10145,7 @@ LegalizerHelper::lowerAbsDiffToSelect(MachineInstr &MI) {
// abdu(lhs, rhs) -> select(ugt(lhs,rhs), sub(lhs,rhs), sub(rhs,lhs))
Register LHSSub = MIRBuilder.buildSub(Ty, LHS, RHS).getReg(0);
Register RHSSub = MIRBuilder.buildSub(Ty, RHS, LHS).getReg(0);
CmpInst::Predicate Pred = (MI.getOpcode() == TargetOpcode::G_ABDS)
CmpInst::Predicate Pred = (MI.getOpcode() == TargetOpcode::G_SABD)
? CmpInst::ICMP_SGT
: CmpInst::ICMP_UGT;
auto ICmp = MIRBuilder.buildICmp(Pred, LLT::scalar(1), LHS, RHS);
Expand All @@ -10157,17 +10157,17 @@ LegalizerHelper::lowerAbsDiffToSelect(MachineInstr &MI) {

LegalizerHelper::LegalizeResult
LegalizerHelper::lowerAbsDiffToMinMax(MachineInstr &MI) {
assert((MI.getOpcode() == TargetOpcode::G_ABDS ||
MI.getOpcode() == TargetOpcode::G_ABDU) &&
"Expected G_ABDS or G_ABDU instruction");
assert((MI.getOpcode() == TargetOpcode::G_SABD ||
MI.getOpcode() == TargetOpcode::G_UABD) &&
"Expected G_SABD or G_UABD instruction");

auto [DstReg, LHS, RHS] = MI.getFirst3Regs();
LLT Ty = MRI.getType(LHS);

// abds(lhs, rhs) -→ sub(smax(lhs, rhs), smin(lhs, rhs))
// abdu(lhs, rhs) -→ sub(umax(lhs, rhs), umin(lhs, rhs))
Register MaxReg, MinReg;
if (MI.getOpcode() == TargetOpcode::G_ABDS) {
if (MI.getOpcode() == TargetOpcode::G_SABD) {
MaxReg = MIRBuilder.buildSMax(Ty, LHS, RHS).getReg(0);
MinReg = MIRBuilder.buildSMin(Ty, LHS, RHS).getReg(0);
} else {
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
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Expand Up @@ -289,7 +289,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.moreElementsToNextPow2(0)
.lower();

getActionDefinitionsBuilder({G_ABDS, G_ABDU})
getActionDefinitionsBuilder({G_SABD, G_UABD})
.legalFor({v8s8, v16s8, v4s16, v8s16, v2s32, v4s32})
.lower();

Expand Down Expand Up @@ -1814,9 +1814,9 @@ bool AArch64LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
case Intrinsic::aarch64_neon_umull:
return LowerBinOp(AArch64::G_UMULL);
case Intrinsic::aarch64_neon_sabd:
return LowerBinOp(TargetOpcode::G_ABDS);
return LowerBinOp(TargetOpcode::G_SABD);
case Intrinsic::aarch64_neon_uabd:
return LowerBinOp(TargetOpcode::G_ABDU);
return LowerBinOp(TargetOpcode::G_UABD);
case Intrinsic::aarch64_neon_abs: {
// Lower the intrinsic to G_ABS.
MIB.buildInstr(TargetOpcode::G_ABS, {MI.getOperand(0)}, {MI.getOperand(2)});
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
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Expand Up @@ -490,7 +490,7 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
.minScalar(ST.hasStdExtZbb(), 0, sXLen)
.lower();

getActionDefinitionsBuilder({G_ABDS, G_ABDU})
getActionDefinitionsBuilder({G_SABD, G_UABD})
.minScalar(ST.hasStdExtZbb(), 0, sXLen)
.lower();

Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
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Expand Up @@ -70,12 +70,12 @@
# DEBUG-NEXT: .. the first uncovered type index: 1, OK
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
#
# DEBUG-NEXT: G_ABDS (opcode [[G_ABDS:[0-9]+]]): 1 type index, 0 imm indices
# DEBUG-NEXT: G_SABD (opcode [[G_SABD:[0-9]+]]): 1 type index, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
#
# DEBUG-NEXT: G_ABDU (opcode [[G_ABDU:[0-9]+]]): 1 type index, 0 imm indices
# DEBUG-NEXT: .. opcode [[G_ABDU]] is aliased to [[G_ABDS]]
# DEBUG-NEXT: G_UABD (opcode [[G_UABD:[0-9]+]]): 1 type index, 0 imm indices
# DEBUG-NEXT: .. opcode [[G_UABD]] is aliased to [[G_SABD]]
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
#
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt
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Expand Up @@ -319,8 +319,6 @@ Key: GC_LABEL: [ 0.00 0.00 ]
Key: GETSEC: [ 0.00 0.00 ]
Key: GF: [ 0.00 0.00 ]
Key: GS_PREFIX: [ 0.00 0.00 ]
Key: G_ABDS: [ 0.00 0.00 ]
Key: G_ABDU: [ 0.00 0.00 ]
Key: G_ABS: [ 0.00 0.00 ]
Key: G_ADD: [ 0.00 0.00 ]
Key: G_ADDRSPACE_CAST: [ 0.00 0.00 ]
Expand Down Expand Up @@ -487,6 +485,7 @@ Key: G_RESET_FPENV: [ 0.00 0.00 ]
Key: G_RESET_FPMODE: [ 0.00 0.00 ]
Key: G_ROTL: [ 0.00 0.00 ]
Key: G_ROTR: [ 0.00 0.00 ]
Key: G_SABD: [ 0.00 0.00 ]
Key: G_SADDE: [ 0.00 0.00 ]
Key: G_SADDO: [ 0.00 0.00 ]
Key: G_SADDSAT: [ 0.00 0.00 ]
Expand Down Expand Up @@ -536,6 +535,7 @@ Key: G_TRUNC: [ 0.00 0.00 ]
Key: G_TRUNC_SSAT_S: [ 0.00 0.00 ]
Key: G_TRUNC_SSAT_U: [ 0.00 0.00 ]
Key: G_TRUNC_USAT_U: [ 0.00 0.00 ]
Key: G_UABD: [ 0.00 0.00 ]
Key: G_UADDE: [ 0.00 0.00 ]
Key: G_UADDO: [ 0.00 0.00 ]
Key: G_UADDSAT: [ 0.00 0.00 ]
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt
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Expand Up @@ -319,8 +319,6 @@ Key: GC_LABEL: [ 0.00 0.00 ]
Key: GETSEC: [ 0.00 0.00 ]
Key: GF: [ 0.00 0.00 ]
Key: GS_PREFIX: [ 0.00 0.00 ]
Key: G_ABDS: [ 0.00 0.00 ]
Key: G_ABDU: [ 0.00 0.00 ]
Key: G_ABS: [ 0.00 0.00 ]
Key: G_ADD: [ 0.00 0.00 ]
Key: G_ADDRSPACE_CAST: [ 0.00 0.00 ]
Expand Down Expand Up @@ -487,6 +485,7 @@ Key: G_RESET_FPENV: [ 0.00 0.00 ]
Key: G_RESET_FPMODE: [ 0.00 0.00 ]
Key: G_ROTL: [ 0.00 0.00 ]
Key: G_ROTR: [ 0.00 0.00 ]
Key: G_SABD: [ 0.00 0.00 ]
Key: G_SADDE: [ 0.00 0.00 ]
Key: G_SADDO: [ 0.00 0.00 ]
Key: G_SADDSAT: [ 0.00 0.00 ]
Expand Down Expand Up @@ -536,6 +535,7 @@ Key: G_TRUNC: [ 0.00 0.00 ]
Key: G_TRUNC_SSAT_S: [ 0.00 0.00 ]
Key: G_TRUNC_SSAT_U: [ 0.00 0.00 ]
Key: G_TRUNC_USAT_U: [ 0.00 0.00 ]
Key: G_UABD: [ 0.00 0.00 ]
Key: G_UADDE: [ 0.00 0.00 ]
Key: G_UADDO: [ 0.00 0.00 ]
Key: G_UADDSAT: [ 0.00 0.00 ]
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
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Expand Up @@ -72,12 +72,12 @@
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
#
# DEBUG-NEXT: G_ABDS (opcode [[G_ABDS:[0-9]+]]): 1 type index, 0 imm indices
# DEBUG-NEXT: G_SABD (opcode [[G_SABD:[0-9]+]]): 1 type index, 0 imm indices
# DEBUG-NEXT:.. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT:.. imm index coverage check SKIPPED: user-defined predicate detected
#
# DEBUG-NEXT:G_ABDU (opcode [[G_ABDU:[0-9]+]]): 1 type index, 0 imm indices
# DEBUG-NEXT:.. opcode [[G_ABDU]] is aliased to [[G_ABDS]]
# DEBUG-NEXT:G_UABD (opcode [[G_UABD:[0-9]+]]): 1 type index, 0 imm indices
# DEBUG-NEXT:.. opcode [[G_UABD]] is aliased to [[G_SABD]]
# DEBUG-NEXT:.. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT:.. imm index coverage check SKIPPED: user-defined predicate detected
#
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-diff-rv32.mir
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Expand Up @@ -41,7 +41,7 @@ body: |
%4:_(s32) = G_ASSERT_SEXT %2, 8
%5:_(s8) = G_TRUNC %3(s32)
%6:_(s8) = G_TRUNC %4(s32)
%7:_(s8) = G_ABDS %5, %6
%7:_(s8) = G_SABD %5, %6
%8:_(s32) = G_ANYEXT %7(s8)
$x10 = COPY %8(s32)
PseudoRET implicit $x10
Expand Down Expand Up @@ -83,7 +83,7 @@ body: |
%4:_(s32) = G_ASSERT_SEXT %2, 16
%5:_(s16) = G_TRUNC %3(s32)
%6:_(s16) = G_TRUNC %4(s32)
%7:_(s16) = G_ABDS %5, %6
%7:_(s16) = G_SABD %5, %6
%8:_(s32) = G_ANYEXT %7(s16)
$x10 = COPY %8(s32)
PseudoRET implicit $x10
Expand Down Expand Up @@ -117,7 +117,7 @@ body: |
; RV32ZBB-NEXT: PseudoRET implicit $x10
%1:_(s32) = COPY $x10
%2:_(s32) = COPY $x11
%3:_(s32) = G_ABDS %1, %2
%3:_(s32) = G_SABD %1, %2
$x10 = COPY %3(s32)
PseudoRET implicit $x10
...
Expand Down Expand Up @@ -153,7 +153,7 @@ body: |
%3:_(s32) = COPY $x10
%4:_(s32) = COPY $x11
%5:_(s64) = G_MERGE_VALUES %3(s32), %4(s32)
%6:_(s64) = G_ABDS %2, %5
%6:_(s64) = G_SABD %2, %5
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
$x10 = COPY %7(s32)
$x11 = COPY %8(s32)
Expand Down Expand Up @@ -196,7 +196,7 @@ body: |
%4:_(s32) = G_ASSERT_ZEXT %2, 8
%5:_(s8) = G_TRUNC %3(s32)
%6:_(s8) = G_TRUNC %4(s32)
%7:_(s8) = G_ABDU %5, %6
%7:_(s8) = G_UABD %5, %6
%8:_(s32) = G_ANYEXT %7(s8)
$x10 = COPY %8(s32)
PseudoRET implicit $x10
Expand Down Expand Up @@ -238,7 +238,7 @@ body: |
%4:_(s32) = G_ASSERT_ZEXT %2, 16
%5:_(s16) = G_TRUNC %3(s32)
%6:_(s16) = G_TRUNC %4(s32)
%7:_(s16) = G_ABDU %5, %6
%7:_(s16) = G_UABD %5, %6
%8:_(s32) = G_ANYEXT %7(s16)
$x10 = COPY %8(s32)
PseudoRET implicit $x10
Expand Down Expand Up @@ -272,7 +272,7 @@ body: |
; RV32ZBB-NEXT: PseudoRET implicit $x10
%1:_(s32) = COPY $x10
%2:_(s32) = COPY $x11
%3:_(s32) = G_ABDU %1, %2
%3:_(s32) = G_UABD %1, %2
$x10 = COPY %3(s32)
PseudoRET implicit $x10
...
Expand Down Expand Up @@ -308,7 +308,7 @@ body: |
%3:_(s32) = COPY $x10
%4:_(s32) = COPY $x11
%5:_(s64) = G_MERGE_VALUES %3(s32), %4(s32)
%6:_(s64) = G_ABDU %2, %5
%6:_(s64) = G_UABD %2, %5
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
$x10 = COPY %7(s32)
$x11 = COPY %8(s32)
Expand Down
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