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[LoongArch][NFC] Pre-commit tests for vector_shuffle which elements from halves or quarters #165665

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[LoongArch][NFC] Pre-commit tests for vector_shuffle which elements from halves or quarters #165665

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173 changes: 173 additions & 0 deletions llvm/test/CodeGen/LoongArch/lsx/shufflevector-halves-quarters.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s

define void @shufflevector_halves_b(ptr %res, ptr %a, ptr %b) nounwind {
; CHECK-LABEL: shufflevector_halves_b:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vld $vr0, $a1, 0
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI0_0)
; CHECK-NEXT: vld $vr1, $a1, %pc_lo12(.LCPI0_0)
; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr0, $vr1
; CHECK-NEXT: vst $vr0, $a0, 0
; CHECK-NEXT: ret
entry:
%va = load <16 x i8>, ptr %a
%vb = load <16 x i8>, ptr %b
%c = shufflevector <16 x i8> %va, <16 x i8> poison, <16 x i32> <i32 0, i32 8, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
store <16 x i8> %c, ptr %res
ret void
}

define void @shufflevector_halves_b_1(ptr %res, ptr %a, ptr %b) nounwind {
; CHECK-LABEL: shufflevector_halves_b_1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vld $vr0, $a1, 0
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI1_0)
; CHECK-NEXT: vld $vr1, $a1, %pc_lo12(.LCPI1_0)
; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr0, $vr1
; CHECK-NEXT: vst $vr0, $a0, 0
; CHECK-NEXT: ret
entry:
%va = load <16 x i8>, ptr %a
%vb = load <16 x i8>, ptr %b
%c = shufflevector <16 x i8> %va, <16 x i8> poison, <16 x i32> <i32 3, i32 11, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
store <16 x i8> %c, ptr %res
ret void
}

define void @shufflevector_halves_b_2(ptr %res, ptr %a, ptr %b) nounwind {
; CHECK-LABEL: shufflevector_halves_b_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vld $vr0, $a1, 0
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI2_0)
; CHECK-NEXT: vld $vr1, $a1, %pc_lo12(.LCPI2_0)
; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr0, $vr1
; CHECK-NEXT: vst $vr0, $a0, 0
; CHECK-NEXT: ret
entry:
%va = load <16 x i8>, ptr %a
%vb = load <16 x i8>, ptr %b
%c = shufflevector <16 x i8> %va, <16 x i8> poison, <16 x i32> <i32 5, i32 13, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
store <16 x i8> %c, ptr %res
ret void
}

define void @shufflevector_halves_b_3(ptr %res, ptr %a, ptr %b) nounwind {
; CHECK-LABEL: shufflevector_halves_b_3:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vld $vr0, $a1, 0
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI3_0)
; CHECK-NEXT: vld $vr1, $a1, %pc_lo12(.LCPI3_0)
; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr0, $vr1
; CHECK-NEXT: vst $vr0, $a0, 0
; CHECK-NEXT: ret
entry:
%va = load <16 x i8>, ptr %a
%vb = load <16 x i8>, ptr %b
%c = shufflevector <16 x i8> %va, <16 x i8> poison, <16 x i32> <i32 6, i32 14, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
store <16 x i8> %c, ptr %res
ret void
}

define void @shufflevector_halves_h(ptr %res, ptr %a, ptr %b) nounwind {
; CHECK-LABEL: shufflevector_halves_h:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vld $vr0, $a1, 0
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI4_0)
; CHECK-NEXT: vld $vr1, $a1, %pc_lo12(.LCPI4_0)
; CHECK-NEXT: vshuf.h $vr1, $vr0, $vr0
; CHECK-NEXT: vst $vr1, $a0, 0
; CHECK-NEXT: ret
entry:
%va = load <8 x i16>, ptr %a
%vb = load <8 x i16>, ptr %b
%c = shufflevector <8 x i16> %va, <8 x i16> poison, <8 x i32> <i32 0, i32 4, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8>
store <8 x i16> %c, ptr %res
ret void
}

define void @shufflevector_halves_h_1(ptr %res, ptr %a, ptr %b) nounwind {
; CHECK-LABEL: shufflevector_halves_h_1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vld $vr0, $a1, 0
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI5_0)
; CHECK-NEXT: vld $vr1, $a1, %pc_lo12(.LCPI5_0)
; CHECK-NEXT: vshuf.h $vr1, $vr0, $vr0
; CHECK-NEXT: vst $vr1, $a0, 0
; CHECK-NEXT: ret
entry:
%va = load <8 x i16>, ptr %a
%vb = load <8 x i16>, ptr %b
%c = shufflevector <8 x i16> %va, <8 x i16> poison, <8 x i32> <i32 3, i32 7, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8>
store <8 x i16> %c, ptr %res
ret void
}

define void @shufflevector_quarters_b(ptr %res, ptr %a, ptr %b) nounwind {
; CHECK-LABEL: shufflevector_quarters_b:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vld $vr0, $a1, 0
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI6_0)
; CHECK-NEXT: vld $vr1, $a1, %pc_lo12(.LCPI6_0)
; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr0, $vr1
; CHECK-NEXT: vst $vr0, $a0, 0
; CHECK-NEXT: ret
entry:
%va = load <16 x i8>, ptr %a
%vb = load <16 x i8>, ptr %b
%c = shufflevector <16 x i8> %va, <16 x i8> poison, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
store <16 x i8> %c, ptr %res
ret void
}

define void @shufflevector_quarters_b_1(ptr %res, ptr %a, ptr %b) nounwind {
; CHECK-LABEL: shufflevector_quarters_b_1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vld $vr0, $a1, 0
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI7_0)
; CHECK-NEXT: vld $vr1, $a1, %pc_lo12(.LCPI7_0)
; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr0, $vr1
; CHECK-NEXT: vst $vr0, $a0, 0
; CHECK-NEXT: ret
entry:
%va = load <16 x i8>, ptr %a
%vb = load <16 x i8>, ptr %b
%c = shufflevector <16 x i8> %va, <16 x i8> poison, <16 x i32> <i32 1, i32 5, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
store <16 x i8> %c, ptr %res
ret void
}

define void @shufflevector_quarters_b_2(ptr %res, ptr %a, ptr %b) nounwind {
; CHECK-LABEL: shufflevector_quarters_b_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vld $vr0, $a1, 0
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI8_0)
; CHECK-NEXT: vld $vr1, $a1, %pc_lo12(.LCPI8_0)
; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr0, $vr1
; CHECK-NEXT: vst $vr0, $a0, 0
; CHECK-NEXT: ret
entry:
%va = load <16 x i8>, ptr %a
%vb = load <16 x i8>, ptr %b
%c = shufflevector <16 x i8> %va, <16 x i8> poison, <16 x i32> <i32 16, i32 6, i32 10, i32 14, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
store <16 x i8> %c, ptr %res
ret void
}

define void @shufflevector_quarters_b_3(ptr %res, ptr %a, ptr %b) nounwind {
; CHECK-LABEL: shufflevector_quarters_b_3:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vld $vr0, $a1, 0
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI9_0)
; CHECK-NEXT: vld $vr1, $a1, %pc_lo12(.LCPI9_0)
; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr0, $vr1
; CHECK-NEXT: vst $vr0, $a0, 0
; CHECK-NEXT: ret
entry:
%va = load <16 x i8>, ptr %a
%vb = load <16 x i8>, ptr %b
%c = shufflevector <16 x i8> %va, <16 x i8> poison, <16 x i32> <i32 3, i32 7, i32 11, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
store <16 x i8> %c, ptr %res
ret void
}
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