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[X86] combinePTESTCC - fold PTESTZ(X,SIGNMASK) -> VTESTPD/PSZ(X,X) on AVX targets #165676

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Merged
merged 3 commits into from
Oct 30, 2025
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[X86] combinePTESTCC - fold PTESTZ(X,SIGNMASK) -> VTESTPD/PSZ(X,X) on AVX targets #165676

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[X86] combinePTESTCC - fold PTESTZ(X,SIGNMASK) -> VTESTPD/PSZ(X,X) on…
RKSimon Oct 30, 2025
547cfae
Freeze duplicated operand
RKSimon Oct 30, 2025
5ab72dc
Merge branch 'main' into x86-ptest-signmask-testp
RKSimon Oct 30, 2025
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20 changes: 20 additions & 0 deletions llvm/lib/Target/X86/X86ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -48860,6 +48860,26 @@ static SDValue combinePTESTCC(SDValue EFLAGS, X86::CondCode &CC,
return DAG.getNode(EFLAGS.getOpcode(), SDLoc(EFLAGS), VT, Op0, Op0);
}

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Do we need to freeze X?

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Nice catch! Yes, we should - all the similar folds in combinePTESTCC seem to be missing that.

// Attempt to convert PTESTZ(X,SIGNMASK) -> VTESTPD/PSZ(X,X) on AVX targets.
if (EFLAGS.getOpcode() == X86ISD::PTEST && Subtarget.hasAVX()) {
KnownBits KnownOp1 = DAG.computeKnownBits(Op1);
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SDM doesn't define element width, while X86ptest defines as i32 vector. Why we check it's 64 here?

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Isn't the i32 the (scalar) result type (for X86SETCC handling?) The isel patterns all use v2i64/v4i64 vectors for the input operands. But I agree, technically PTEST shouldn't care about vector element type but there's never been any need to make it work generically.

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Yeah, I took it as a element type 🤦‍♀️

assert(KnownOp1.getBitWidth() == 64 &&
"Illegal PTEST vector element width");
if (KnownOp1.isConstant()) {
const APInt &Mask = KnownOp1.getConstant();
if (Mask.isSignMask()) {
MVT FpVT = MVT::getVectorVT(MVT::f64, OpVT.getSizeInBits() / 64);
Op0 = DAG.getBitcast(FpVT, DAG.getFreeze(Op0));
return DAG.getNode(X86ISD::TESTP, SDLoc(EFLAGS), VT, Op0, Op0);
}
if (Mask.isSplat(32) && Mask.trunc(32).isSignMask()) {
MVT FpVT = MVT::getVectorVT(MVT::f32, OpVT.getSizeInBits() / 32);
Op0 = DAG.getBitcast(FpVT, DAG.getFreeze(Op0));
return DAG.getNode(X86ISD::TESTP, SDLoc(EFLAGS), VT, Op0, Op0);
}
}
}

// TESTZ(OR(LO(X),HI(X)),OR(LO(Y),HI(Y))) -> TESTZ(X,Y)
// TODO: Add COND_NE handling?
if (CC == X86::COND_E && OpVT.is128BitVector() && Subtarget.hasAVX()) {
Expand Down
84 changes: 18 additions & 66 deletions llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll
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Expand Up @@ -875,28 +875,12 @@ define i1 @mask_v8i32(<8 x i32> %a0) {
; SSE41-NEXT: sete %al
; SSE41-NEXT: retq
;
; AVX1-LABEL: mask_v8i32:
; AVX1: # %bb.0:
; AVX1-NEXT: vptest {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0
; AVX1-NEXT: sete %al
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
; AVX2-LABEL: mask_v8i32:
; AVX2: # %bb.0:
; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [9223372039002259456,9223372039002259456,9223372039002259456,9223372039002259456]
; AVX2-NEXT: vptest %ymm1, %ymm0
; AVX2-NEXT: sete %al
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
;
; AVX512-LABEL: mask_v8i32:
; AVX512: # %bb.0:
; AVX512-NEXT: vpbroadcastq {{.*#+}} ymm1 = [9223372039002259456,9223372039002259456,9223372039002259456,9223372039002259456]
; AVX512-NEXT: vptest %ymm1, %ymm0
; AVX512-NEXT: sete %al
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq
; AVX-LABEL: mask_v8i32:
; AVX: # %bb.0:
; AVX-NEXT: vtestps %ymm0, %ymm0
; AVX-NEXT: sete %al
; AVX-NEXT: vzeroupper
; AVX-NEXT: retq
%1 = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> %a0)
%2 = and i32 %1, 2147483648
%3 = icmp eq i32 %2, 0
Expand Down Expand Up @@ -965,28 +949,12 @@ define i1 @signtest_v8i32(<8 x i32> %a0) {
; SSE41-NEXT: sete %al
; SSE41-NEXT: retq
;
; AVX1-LABEL: signtest_v8i32:
; AVX1: # %bb.0:
; AVX1-NEXT: vptest {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0
; AVX1-NEXT: sete %al
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
; AVX2-LABEL: signtest_v8i32:
; AVX2: # %bb.0:
; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [9223372039002259456,9223372039002259456,9223372039002259456,9223372039002259456]
; AVX2-NEXT: vptest %ymm1, %ymm0
; AVX2-NEXT: sete %al
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
;
; AVX512-LABEL: signtest_v8i32:
; AVX512: # %bb.0:
; AVX512-NEXT: vpbroadcastq {{.*#+}} ymm1 = [9223372039002259456,9223372039002259456,9223372039002259456,9223372039002259456]
; AVX512-NEXT: vptest %ymm1, %ymm0
; AVX512-NEXT: sete %al
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq
; AVX-LABEL: signtest_v8i32:
; AVX: # %bb.0:
; AVX-NEXT: vtestps %ymm0, %ymm0
; AVX-NEXT: sete %al
; AVX-NEXT: vzeroupper
; AVX-NEXT: retq
%1 = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> %a0)
%2 = icmp sgt i32 %1, -1
ret i1 %2
Expand All @@ -1010,28 +978,12 @@ define i1 @signtest_v4i64(<4 x i64> %a0) {
; SSE41-NEXT: sete %al
; SSE41-NEXT: retq
;
; AVX1-LABEL: signtest_v4i64:
; AVX1: # %bb.0:
; AVX1-NEXT: vptest {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0
; AVX1-NEXT: sete %al
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
; AVX2-LABEL: signtest_v4i64:
; AVX2: # %bb.0:
; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
; AVX2-NEXT: vptest %ymm1, %ymm0
; AVX2-NEXT: sete %al
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
;
; AVX512-LABEL: signtest_v4i64:
; AVX512: # %bb.0:
; AVX512-NEXT: vpbroadcastq {{.*#+}} ymm1 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
; AVX512-NEXT: vptest %ymm1, %ymm0
; AVX512-NEXT: sete %al
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq
; AVX-LABEL: signtest_v4i64:
; AVX: # %bb.0:
; AVX-NEXT: vtestpd %ymm0, %ymm0
; AVX-NEXT: sete %al
; AVX-NEXT: vzeroupper
; AVX-NEXT: retq
%1 = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> %a0)
%2 = icmp sgt i64 %1, -1
ret i1 %2
Expand Down
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