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[AMDGPU][True16][CodeGen] lower flat_d16_saddr_t16 to saddr inst #166603

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Merged
merged 1 commit into from
Nov 14, 2025
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[AMDGPU][True16][CodeGen] lower flat_d16_saddr_t16 to saddr inst #166603

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14 changes: 12 additions & 2 deletions llvm/lib/Target/AMDGPU/FLATInstructions.td
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Original file line number Diff line number Diff line change
Expand Up @@ -262,8 +262,18 @@ multiclass FLAT_Flat_Load_Pseudo<string opName, RegisterOperand regClass = AVLdS

multiclass FLAT_Flat_Load_Pseudo_t16<string opName> {
defm "" : FLAT_Flat_Load_Pseudo<opName, AVLdSt_32, 1>;
let True16Predicate = UseRealTrue16Insts in
defm _t16 : FLAT_Flat_Load_Pseudo<opName#"_t16", VGPROp_16>, True16D16Table<NAME#"_HI", NAME>;

defvar Name16 = opName#"_t16";
let True16Predicate = UseRealTrue16Insts in {
def _t16 : FLAT_Load_Pseudo<Name16, VGPROp_16>,
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@rampitec rampitec Nov 11, 2025

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This should not have HasFlatGVSMode, only SADDR form? Just like above in the FLAT_Flat_Load_Pseudo.

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@broxigarchen broxigarchen Nov 13, 2025

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Agree

GlobalSaddrTable<0, Name16>,
True16D16Table<NAME#"_HI", NAME>;

let OtherPredicates = [HasFlatGVSMode] in
def _t16_SADDR : FLAT_Load_Pseudo<Name16, VGPROp_16, 0, 1, 1>,
GlobalSaddrTable<1, Name16>,
True16D16Table<NAME#"_HI_SADDR", NAME#"_SADDR">;
}
}

class FLAT_Store_Pseudo <string opName, RegisterOperand vdataClass,
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