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[BOLT][AArch64] Fix printing of relocation types #166621

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Merged
merged 1 commit into from
Nov 5, 2025
Merged

[BOLT][AArch64] Fix printing of relocation types #166621

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38 changes: 6 additions & 32 deletions bolt/lib/Core/Relocation.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1018,41 +1018,15 @@ void Relocation::print(raw_ostream &OS) const {
default:
OS << "RType:" << Twine::utohexstr(Type);
break;

case Triple::aarch64: {
static const char *const AArch64RelocNames[] = {
#define ELF_RELOC(name, value) #name,
#include "llvm/BinaryFormat/ELFRelocs/AArch64.def"
#undef ELF_RELOC
};
assert(Type < ArrayRef(AArch64RelocNames).size());
OS << AArch64RelocNames[Type];
} break;

case Triple::aarch64:
OS << object::getELFRelocationTypeName(ELF::EM_AARCH64, Type);
break;
case Triple::riscv64:
// RISC-V relocations are not sequentially numbered so we cannot use an
// array
switch (Type) {
default:
llvm_unreachable("illegal RISC-V relocation");
#define ELF_RELOC(name, value) \
case value: \
OS << #name; \
OS << object::getELFRelocationTypeName(ELF::EM_RISCV, Type);
break;
#include "llvm/BinaryFormat/ELFRelocs/RISCV.def"
#undef ELF_RELOC
}
case Triple::x86_64:
OS << object::getELFRelocationTypeName(ELF::EM_X86_64, Type);
break;

case Triple::x86_64: {
static const char *const X86RelocNames[] = {
#define ELF_RELOC(name, value) #name,
#include "llvm/BinaryFormat/ELFRelocs/x86_64.def"
#undef ELF_RELOC
};
assert(Type < ArrayRef(X86RelocNames).size());
OS << X86RelocNames[Type];
} break;
}
OS << ", 0x" << Twine::utohexstr(Offset);
if (Symbol) {
Expand Down
24 changes: 24 additions & 0 deletions bolt/test/AArch64/relocation-type-print.s
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Original file line number Diff line number Diff line change
@@ -0,0 +1,24 @@
## Verify that llvm-bolt correctly prints relocation types.

# REQUIRES: system-linux

# RUN: %clang %cflags -nostartfiles %s -o %t.exe -Wl,-q,--no-relax
# RUN: llvm-bolt %t.exe --print-cfg --print-relocations -o %t.bolt \
# RUN: | FileCheck %s

.section .text
.align 4
.globl _start
.type _start, %function
_start:

adrp x0, _start
# CHECK: adrp
# CHECK-SAME: R_AARCH64_ADR_PREL_PG_HI21

add x0, x0, :lo12:_start
# CHECK-NEXT: add
# CHECK-SAME: R_AARCH64_ADD_ABS_LO12_NC

ret
.size _start, .-_start
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