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AMDGPU: Replace some undef uses in tests #166813

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Merged
merged 1 commit into from
Nov 6, 2025
Merged

AMDGPU: Replace some undef uses in tests #166813

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8 changes: 4 additions & 4 deletions llvm/test/CodeGen/AMDGPU/branch-relaxation-gfx1250.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -280,7 +280,7 @@ bb0:
br i1 %tmp, label %bb2, label %bb3

bb2:
store volatile i32 17, ptr addrspace(1) undef
store volatile i32 17, ptr addrspace(1) poison
br label %bb4

bb3:
Expand Down Expand Up @@ -375,7 +375,7 @@ bb0:
br i1 %cmp0, label %bb2, label %bb1

bb1:
%val = load volatile i32, ptr addrspace(4) undef
%val = load volatile i32, ptr addrspace(4) poison
%cmp1 = icmp eq i32 %val, 3
br i1 %cmp1, label %bb3, label %bb2

Expand Down Expand Up @@ -512,7 +512,7 @@ loop_body:
br label %loop

ret:
store volatile i32 7, ptr addrspace(1) undef
store volatile i32 7, ptr addrspace(1) poison
ret void
}

Expand Down Expand Up @@ -622,7 +622,7 @@ bb14: ; preds = %bb13, %bb9
br label %bb19

bb19: ; preds = %bb14, %bb13, %bb9
%tmp20 = phi i32 [ undef, %bb9 ], [ undef, %bb13 ], [ %tmp18, %bb14 ]
%tmp20 = phi i32 [ poison, %bb9 ], [ poison, %bb13 ], [ %tmp18, %bb14 ]
%tmp21 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 %arg5
store i32 %tmp20, ptr addrspace(1) %tmp21, align 4
ret void
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
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Expand Up @@ -263,7 +263,7 @@ define amdgpu_ps float @flat_xchg_saddr_i32_rtn_neg2048(ptr inreg %sbase, i32 %v
; Uniformity edge cases
; --------------------------------------------------------------------------------

@ptr.in.lds = internal addrspace(3) global ptr undef
@ptr.in.lds = internal addrspace(3) global ptr poison

; Base pointer is uniform, but also in VGPRs
define amdgpu_ps float @flat_xchg_saddr_uniform_ptr_in_vgprs_rtn(i32 %voffset, i32 %data) {
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/flat-saddr-store.ll
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Expand Up @@ -54,7 +54,7 @@ define amdgpu_ps void @flat_store_saddr_i8_zext_vgpr_offset_neg2048(ptr inreg %s
; Uniformity edge cases
; --------------------------------------------------------------------------------

@ptr.in.lds = internal addrspace(3) global ptr undef
@ptr.in.lds = internal addrspace(3) global ptr poison

; Base pointer is uniform, but also in VGPRs
define amdgpu_ps void @flat_store_saddr_uniform_ptr_in_vgprs(i32 %voffset, i8 %data) {
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AMDGPU/scheduler-rp-calc-one-successor-two-predecessors-bug.ll
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Expand Up @@ -46,7 +46,7 @@ define amdgpu_ps void @_amdgpu_ps_main(float %arg) {
; GFX900-NEXT: s_mov_b64 exec, 0
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: v_mov_b32_e32 v1, 0
; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_mov_b32_e32 v2, v1
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@shiltian shiltian Nov 6, 2025

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This change is unexpected though

; GFX900-NEXT: .LBB0_5: ; %bb6
; GFX900-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX900-NEXT: s_waitcnt vmcnt(0)
Expand Down Expand Up @@ -75,7 +75,7 @@ bb5:
bb6:
%i7 = phi float [ 0.000000e+00, %bb5 ], [ %i3, %bb1 ]
%i8 = phi float [ 0.000000e+00, %bb5 ], [ 1.000000e+00, %bb1 ]
%i9 = phi float [ undef, %bb5 ], [ %i4, %bb1 ]
%i9 = phi float [ poison, %bb5 ], [ %i4, %bb1 ]
%i10 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float 0.000000e+00, float %i7)
%i11 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %i8, float %i9)
call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 0, <2 x half> %i10, <2 x half> %i11, i1 false, i1 false)
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
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Expand Up @@ -655,7 +655,7 @@ bb:
br label %bb5

bb5: ; preds = %bb5.backedge, %bb
%tmp4.i.sroa.0.0 = phi <9 x double> [ undef, %bb ], [ %tmp4.i.sroa.0.1, %bb5.backedge ]
%tmp4.i.sroa.0.0 = phi <9 x double> [ poison, %bb ], [ %tmp4.i.sroa.0.1, %bb5.backedge ]
%tmp14.1.i = load i32, ptr inttoptr (i64 128 to ptr), align 128
store i32 0, ptr addrspace(5) null, align 4
%tmp14.2.i = load i32, ptr inttoptr (i64 128 to ptr), align 128
Expand Down