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[NFC][PowerPC] Pre-commit adding test case: use millicode for memmove #166961

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Merged
merged 1 commit into from
Nov 10, 2025
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[NFC][PowerPC] Pre-commit adding test case: use millicode for memmove #166961

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56 changes: 56 additions & 0 deletions llvm/test/CodeGen/PowerPC/milicode32.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -69,3 +69,59 @@ entry:
}

declare i32 @strlen(ptr noundef) nounwind

define ptr @test_memmove(ptr noundef %destination, ptr noundef %source, i32 noundef %num) #0 {
; CHECK-AIX-32-P9-LABEL: test_memmove:
; CHECK-AIX-32-P9: # %bb.0: # %entry
; CHECK-AIX-32-P9-NEXT: mflr r0
; CHECK-AIX-32-P9-NEXT: stwu r1, -80(r1)
; CHECK-AIX-32-P9-NEXT: stw r0, 88(r1)
; CHECK-AIX-32-P9-NEXT: stw r31, 76(r1) # 4-byte Folded Spill
; CHECK-AIX-32-P9-NEXT: mr r31, r3
; CHECK-AIX-32-P9-NEXT: stw r3, 72(r1)
; CHECK-AIX-32-P9-NEXT: stw r4, 68(r1)
; CHECK-AIX-32-P9-NEXT: stw r5, 64(r1)
; CHECK-AIX-32-P9-NEXT: bl .___memmove[PR]
; CHECK-AIX-32-P9-NEXT: nop
; CHECK-AIX-32-P9-NEXT: mr r3, r31
; CHECK-AIX-32-P9-NEXT: lwz r31, 76(r1) # 4-byte Folded Reload
; CHECK-AIX-32-P9-NEXT: addi r1, r1, 80
; CHECK-AIX-32-P9-NEXT: lwz r0, 8(r1)
; CHECK-AIX-32-P9-NEXT: mtlr r0
; CHECK-AIX-32-P9-NEXT: blr
;
; CHECK-LINUX32-P9-LABEL: test_memmove:
; CHECK-LINUX32-P9: # %bb.0: # %entry
; CHECK-LINUX32-P9-NEXT: mflr r0
; CHECK-LINUX32-P9-NEXT: stwu r1, -32(r1)
; CHECK-LINUX32-P9-NEXT: stw r0, 36(r1)
; CHECK-LINUX32-P9-NEXT: .cfi_def_cfa_offset 32
; CHECK-LINUX32-P9-NEXT: .cfi_offset lr, 4
; CHECK-LINUX32-P9-NEXT: .cfi_offset r30, -8
; CHECK-LINUX32-P9-NEXT: stw r30, 24(r1) # 4-byte Folded Spill
; CHECK-LINUX32-P9-NEXT: mr r30, r3
; CHECK-LINUX32-P9-NEXT: stw r3, 20(r1)
; CHECK-LINUX32-P9-NEXT: stw r4, 16(r1)
; CHECK-LINUX32-P9-NEXT: stw r5, 12(r1)
; CHECK-LINUX32-P9-NEXT: bl memmove
; CHECK-LINUX32-P9-NEXT: mr r3, r30
; CHECK-LINUX32-P9-NEXT: lwz r30, 24(r1) # 4-byte Folded Reload
; CHECK-LINUX32-P9-NEXT: lwz r0, 36(r1)
; CHECK-LINUX32-P9-NEXT: addi r1, r1, 32
; CHECK-LINUX32-P9-NEXT: mtlr r0
; CHECK-LINUX32-P9-NEXT: blr
entry:
%destination.addr = alloca ptr, align 4
%source.addr = alloca ptr, align 4
%num.addr = alloca i32, align 4
store ptr %destination, ptr %destination.addr, align 4
store ptr %source, ptr %source.addr, align 4
store i32 %num, ptr %num.addr, align 4
%0 = load ptr, ptr %destination.addr, align 4
%1 = load ptr, ptr %source.addr, align 4
%2 = load i32, ptr %num.addr, align 4
call void @llvm.memmove.p0.p0.i32(ptr align 1 %0, ptr align 1 %1, i32 %2, i1 false)
ret ptr %0
}

declare void @llvm.memmove.p0.p0.i32(ptr writeonly captures(none), ptr readonly captures(none), i32, i1 immarg)
79 changes: 79 additions & 0 deletions llvm/test/CodeGen/PowerPC/milicode64.ll
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Expand Up @@ -100,3 +100,82 @@ entry:
}

declare i64 @strlen(ptr noundef) nounwind

define ptr @test_memmove(ptr noundef %destination, ptr noundef %source, i64 noundef %num) #0 {
; CHECK-LE-P9-LABEL: test_memmove:
; CHECK-LE-P9: # %bb.0: # %entry
; CHECK-LE-P9-NEXT: mflr r0
; CHECK-LE-P9-NEXT: .cfi_def_cfa_offset 80
; CHECK-LE-P9-NEXT: .cfi_offset lr, 16
; CHECK-LE-P9-NEXT: .cfi_offset r30, -16
; CHECK-LE-P9-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-LE-P9-NEXT: stdu r1, -80(r1)
; CHECK-LE-P9-NEXT: std r0, 96(r1)
; CHECK-LE-P9-NEXT: mr r30, r3
; CHECK-LE-P9-NEXT: std r3, 56(r1)
; CHECK-LE-P9-NEXT: std r4, 48(r1)
; CHECK-LE-P9-NEXT: std r5, 40(r1)
; CHECK-LE-P9-NEXT: bl memmove
; CHECK-LE-P9-NEXT: nop
; CHECK-LE-P9-NEXT: mr r3, r30
; CHECK-LE-P9-NEXT: addi r1, r1, 80
; CHECK-LE-P9-NEXT: ld r0, 16(r1)
; CHECK-LE-P9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-LE-P9-NEXT: mtlr r0
; CHECK-LE-P9-NEXT: blr
;
; CHECK-BE-P9-LABEL: test_memmove:
; CHECK-BE-P9: # %bb.0: # %entry
; CHECK-BE-P9-NEXT: mflr r0
; CHECK-BE-P9-NEXT: stdu r1, -160(r1)
; CHECK-BE-P9-NEXT: std r0, 176(r1)
; CHECK-BE-P9-NEXT: .cfi_def_cfa_offset 160
; CHECK-BE-P9-NEXT: .cfi_offset lr, 16
; CHECK-BE-P9-NEXT: .cfi_offset r30, -16
; CHECK-BE-P9-NEXT: std r30, 144(r1) # 8-byte Folded Spill
; CHECK-BE-P9-NEXT: mr r30, r3
; CHECK-BE-P9-NEXT: std r3, 136(r1)
; CHECK-BE-P9-NEXT: std r4, 128(r1)
; CHECK-BE-P9-NEXT: std r5, 120(r1)
; CHECK-BE-P9-NEXT: bl memmove
; CHECK-BE-P9-NEXT: nop
; CHECK-BE-P9-NEXT: mr r3, r30
; CHECK-BE-P9-NEXT: ld r30, 144(r1) # 8-byte Folded Reload
; CHECK-BE-P9-NEXT: addi r1, r1, 160
; CHECK-BE-P9-NEXT: ld r0, 16(r1)
; CHECK-BE-P9-NEXT: mtlr r0
; CHECK-BE-P9-NEXT: blr
;
; CHECK-AIX-64-P9-LABEL: test_memmove:
; CHECK-AIX-64-P9: # %bb.0: # %entry
; CHECK-AIX-64-P9-NEXT: mflr r0
; CHECK-AIX-64-P9-NEXT: stdu r1, -144(r1)
; CHECK-AIX-64-P9-NEXT: std r0, 160(r1)
; CHECK-AIX-64-P9-NEXT: std r31, 136(r1) # 8-byte Folded Spill
; CHECK-AIX-64-P9-NEXT: mr r31, r3
; CHECK-AIX-64-P9-NEXT: std r3, 128(r1)
; CHECK-AIX-64-P9-NEXT: std r4, 120(r1)
; CHECK-AIX-64-P9-NEXT: std r5, 112(r1)
; CHECK-AIX-64-P9-NEXT: bl .memmove[PR]
; CHECK-AIX-64-P9-NEXT: nop
; CHECK-AIX-64-P9-NEXT: mr r3, r31
; CHECK-AIX-64-P9-NEXT: ld r31, 136(r1) # 8-byte Folded Reload
; CHECK-AIX-64-P9-NEXT: addi r1, r1, 144
; CHECK-AIX-64-P9-NEXT: ld r0, 16(r1)
; CHECK-AIX-64-P9-NEXT: mtlr r0
; CHECK-AIX-64-P9-NEXT: blr
entry:
%destination.addr = alloca ptr, align 8
%source.addr = alloca ptr, align 8
%num.addr = alloca i64, align 8
store ptr %destination, ptr %destination.addr, align 8
store ptr %source, ptr %source.addr, align 8
store i64 %num, ptr %num.addr, align 8
%0 = load ptr, ptr %destination.addr, align 8
%1 = load ptr, ptr %source.addr, align 8
%2 = load i64, ptr %num.addr, align 8
call void @llvm.memmove.p0.p0.i64(ptr align 1 %0, ptr align 1 %1, i64 %2, i1 false)
ret ptr %0
}

declare void @llvm.memmove.p0.p0.i32(ptr writeonly captures(none), ptr readonly captures(none), i32, i1 immarg)