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[Target] Fix misleading indentation (NFC) #167206

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Merged
merged 1 commit into from
Nov 9, 2025
Merged

[Target] Fix misleading indentation (NFC) #167206

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2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -26050,7 +26050,7 @@ static SDValue performCSELCombine(SDNode *N,
// CSEL 0, cttz(X), eq(X, 0) -> AND cttz bitwidth-1
// CSEL cttz(X), 0, ne(X, 0) -> AND cttz bitwidth-1
if (SDValue Folded = foldCSELofCTTZ(N, DAG))
return Folded;
return Folded;

// CSEL a, b, cc, SUBS(x, y) -> CSEL a, b, swapped(cc), SUBS(y, x)
// if SUB(y, x) already exists and we can produce a swapped predicate for cc.
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10 changes: 5 additions & 5 deletions llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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Expand Up @@ -1402,7 +1402,7 @@ static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm));
} else {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(U));
}

Expand Down Expand Up @@ -1922,7 +1922,7 @@ static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
imm |= fieldFromInstruction(Insn, 24, 1) << 1;
if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
true, 4, Inst, Decoder))
Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
return S;
}

Expand Down Expand Up @@ -3703,17 +3703,17 @@ static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;

if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
return MCDisassembler::Fail;
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createReg(ARM::SP));
if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
return MCDisassembler::Fail;
return MCDisassembler::Fail;
} else if (Inst.getOpcode() == ARM::tADDspr) {
unsigned Rm = fieldFromInstruction(Insn, 3, 4);

Inst.addOperand(MCOperand::createReg(ARM::SP));
Inst.addOperand(MCOperand::createReg(ARM::SP));
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
return MCDisassembler::Fail;
}

return S;
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2 changes: 1 addition & 1 deletion llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp
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Expand Up @@ -198,7 +198,7 @@ bool HexagonOptAddrMode::canRemoveAddasl(NodeAddr<StmtNode *> AddAslSN,
// Reaching Def to an offset register can't be a phi.
if ((OffsetRegDN.Addr->getFlags() & NodeAttrs::PhiRef) &&
MI.getParent() != UseMI.getParent())
return false;
return false;

const MCInstrDesc &UseMID = UseMI.getDesc();
if ((!UseMID.mayLoad() && !UseMID.mayStore()) ||
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4 changes: 2 additions & 2 deletions llvm/lib/Target/Mips/Mips16InstrInfo.cpp
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Expand Up @@ -405,9 +405,9 @@ unsigned Mips16InstrInfo::loadImmediate(unsigned FrameReg, int64_t Imm,
}
if (SecondRegSaved)
copyPhysReg(MBB, II, DL, SecondRegSavedTo, SecondRegSaved, true);
} else {
Available.reset(SpReg);
}
else
Available.reset(SpReg);
copyPhysReg(MBB, II, DL, SpReg, Mips::SP, false);
BuildMI(MBB, II, DL, get(Mips::AdduRxRyRz16), Reg)
.addReg(SpReg, RegState::Kill)
Expand Down