Skip to content

[AMDGPU] Verify dominance when rewriting spills to registers #167347

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 1 commit into
base: main
Choose a base branch
from
+2,172 −4
Open

[AMDGPU] Verify dominance when rewriting spills to registers #167347

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
92 changes: 88 additions & 4 deletions llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -30,6 +30,7 @@
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/LiveRegMatrix.h"
#include "llvm/CodeGen/LiveStacks.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/VirtRegMap.h"
Expand Down Expand Up @@ -58,6 +59,7 @@ class AMDGPURewriteAGPRCopyMFMAImpl {
LiveIntervals &LIS;
LiveStacks &LSS;
const RegisterClassInfo &RegClassInfo;
MachineDominatorTree &MDT;

bool attemptReassignmentsToAGPR(SmallSetVector<Register, 4> &InterferingRegs,
MCPhysReg PrefPhysReg) const;
Expand All @@ -66,10 +68,11 @@ class AMDGPURewriteAGPRCopyMFMAImpl {
AMDGPURewriteAGPRCopyMFMAImpl(MachineFunction &MF, VirtRegMap &VRM,
LiveRegMatrix &LRM, LiveIntervals &LIS,
LiveStacks &LSS,
const RegisterClassInfo &RegClassInfo)
const RegisterClassInfo &RegClassInfo,
MachineDominatorTree &MDT)
: MF(MF), ST(MF.getSubtarget<GCNSubtarget>()), TII(*ST.getInstrInfo()),
TRI(*ST.getRegisterInfo()), MRI(MF.getRegInfo()), VRM(VRM), LRM(LRM),
LIS(LIS), LSS(LSS), RegClassInfo(RegClassInfo) {}
LIS(LIS), LSS(LSS), RegClassInfo(RegClassInfo), MDT(MDT) {}

bool isRewriteCandidate(const MachineInstr &MI) const {
return TII.isMAI(MI) && AMDGPU::getMFMASrcCVDstAGPROp(MI.getOpcode()) != -1;
Expand Down Expand Up @@ -515,6 +518,82 @@ void AMDGPURewriteAGPRCopyMFMAImpl::eliminateSpillsOfReassignedVGPRs() const {
if (SpillReferences == SpillSlotReferences.end())
continue;

// For each spill reload, every path from entry to the reload must pass
// through at least one spill store to the same stack slot.
SmallVector<MachineInstr *, 4> Stores, Loads;
Stores.reserve(SpillReferences->second.size());
Loads.reserve(SpillReferences->second.size());
for (MachineInstr *MI : SpillReferences->second) {
if (MI->mayStore())
Stores.push_back(MI);
else if (MI->mayLoad())
Loads.push_back(MI);
}

SmallPtrSet<MachineBasicBlock *, 4> StoreBlocks;
for (MachineInstr *S : Stores)
if (MDT.isReachableFromEntry(S->getParent()))
StoreBlocks.insert(S->getParent());

if (StoreBlocks.empty()) {
LLVM_DEBUG(dbgs() << "Skipping " << printReg(Slot, &TRI)
<< ": no reachable stores\n");
continue;
}

// Compute blocks reachable from entry without passing through a store
// block.
SmallPtrSet<MachineBasicBlock *, 16> StoreFreeReachable;
SmallVector<MachineBasicBlock *, 16> Worklist;

MachineBasicBlock &EntryMBB = MF.front();
Worklist.push_back(&EntryMBB);
StoreFreeReachable.insert(&EntryMBB);

while (!Worklist.empty()) {
MachineBasicBlock *MBB = Worklist.pop_back_val();
if (StoreBlocks.contains(MBB))
continue;

for (MachineBasicBlock *Succ : MBB->successors()) {
if (StoreFreeReachable.insert(Succ).second)
Worklist.push_back(Succ);
}
}

auto IsLoadJointlyDominatedByStores = [&](MachineInstr *LoadMI) -> bool {
MachineBasicBlock *LoadMBB = LoadMI->getParent();
if (!MDT.isReachableFromEntry(LoadMBB))
return true;

// Check if every path passed through a store block.
if (!StoreFreeReachable.contains(LoadMBB))
return true;

// Otherwise, there exists a path to this block that has not seen any
// store yet. We must ensure that within this block there is a store to
// this slot before the load.
for (MachineInstr &MI : *LoadMBB) {
if (&MI == LoadMI)
break;
if (MI.mayStore()) {
for (MachineOperand &MO : MI.operands()) {
if (MO.isFI() && MO.getIndex() == Slot)
return true;
}
}
}

return false;
};

if (!llvm::all_of(Loads, IsLoadJointlyDominatedByStores)) {
LLVM_DEBUG(
dbgs() << "Skipping " << printReg(Slot, &TRI)
<< ": some reachable load not jointly dominated by stores\n");
continue;
}

const TargetRegisterClass *RC = LSS.getIntervalRegClass(Slot);

LLVM_DEBUG(dbgs() << "Trying to eliminate " << printReg(Slot, &TRI)
Expand Down Expand Up @@ -603,11 +682,13 @@ class AMDGPURewriteAGPRCopyMFMALegacy : public MachineFunctionPass {
AU.addRequired<VirtRegMapWrapperLegacy>();
AU.addRequired<LiveRegMatrixWrapperLegacy>();
AU.addRequired<LiveStacksWrapperLegacy>();
AU.addRequired<MachineDominatorTreeWrapperPass>();

AU.addPreserved<LiveIntervalsWrapperPass>();
AU.addPreserved<VirtRegMapWrapperLegacy>();
AU.addPreserved<LiveRegMatrixWrapperLegacy>();
AU.addPreserved<LiveStacksWrapperLegacy>();
AU.addPreserved<MachineDominatorTreeWrapperPass>();

AU.setPreservesAll();
MachineFunctionPass::getAnalysisUsage(AU);
Expand All @@ -622,6 +703,7 @@ INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperLegacy)
INITIALIZE_PASS_DEPENDENCY(LiveRegMatrixWrapperLegacy)
INITIALIZE_PASS_DEPENDENCY(LiveStacksWrapperLegacy)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
INITIALIZE_PASS_END(AMDGPURewriteAGPRCopyMFMALegacy, DEBUG_TYPE,
"AMDGPU Rewrite AGPR-Copy-MFMA", false, false)

Expand All @@ -641,7 +723,8 @@ bool AMDGPURewriteAGPRCopyMFMALegacy::runOnMachineFunction(
auto &LRM = getAnalysis<LiveRegMatrixWrapperLegacy>().getLRM();
auto &LIS = getAnalysis<LiveIntervalsWrapperPass>().getLIS();
auto &LSS = getAnalysis<LiveStacksWrapperLegacy>().getLS();
AMDGPURewriteAGPRCopyMFMAImpl Impl(MF, VRM, LRM, LIS, LSS, RegClassInfo);
auto &MDT = getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
AMDGPURewriteAGPRCopyMFMAImpl Impl(MF, VRM, LRM, LIS, LSS, RegClassInfo, MDT);
return Impl.run(MF);
}

Expand All @@ -652,10 +735,11 @@ AMDGPURewriteAGPRCopyMFMAPass::run(MachineFunction &MF,
LiveRegMatrix &LRM = MFAM.getResult<LiveRegMatrixAnalysis>(MF);
LiveIntervals &LIS = MFAM.getResult<LiveIntervalsAnalysis>(MF);
LiveStacks &LSS = MFAM.getResult<LiveStacksAnalysis>(MF);
MachineDominatorTree &MDT = MFAM.getResult<MachineDominatorTreeAnalysis>(MF);
RegisterClassInfo RegClassInfo;
RegClassInfo.runOnMachineFunction(MF);

AMDGPURewriteAGPRCopyMFMAImpl Impl(MF, VRM, LRM, LIS, LSS, RegClassInfo);
AMDGPURewriteAGPRCopyMFMAImpl Impl(MF, VRM, LRM, LIS, LSS, RegClassInfo, MDT);
if (!Impl.run(MF))
return PreservedAnalyses::all();
auto PA = getMachineFunctionPassPreservedAnalyses();
Expand Down
Loading
Loading