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[AMDGPU] Analyze REG_SEQUENCE To Remove Redundant CMP Instructions #167364

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[AMDGPU] Analyze REG_SEQUENCE To Remove Redundant CMP Instructions #167364

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linuxrocks123 Nov 10, 2025
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31 changes: 31 additions & 0 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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Expand Up @@ -1313,6 +1313,34 @@ Register SIInstrInfo::insertNE(MachineBasicBlock *MBB,
return Reg;
}

MachineInstr *
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@LU-JOHN LU-JOHN Nov 10, 2025 •
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I think it would be helpful to add a comment describing what is being done. Something like:

For a 64-bit value defined by a REG_SEQUENCE with half of the result being 0, find the instruction that defines exactly the bits in the other half.

SIInstrInfo::pierceThroughRegSequence(const MachineInstr &MI) const {
if (MI.getOpcode() != AMDGPU::REG_SEQUENCE || MI.getNumOperands() != 5)
return nullptr;

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@LU-JOHN LU-JOHN Nov 10, 2025

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Check if MI has wrong number of operands.

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@linuxrocks123 linuxrocks123 Nov 10, 2025

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Done

const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
int64_t SubRegValues[2];
bool SubRegIsConst[2];
MachineInstr *RealDefs[2];
for (unsigned I : {2, 4}) {
unsigned ArrayIdx = MI.getOperand(I).getImm() == AMDGPU::sub0 ? 0 : 1;
Register Subreg = MI.getOperand(I - 1).getReg();
RealDefs[ArrayIdx] = MRI.getUniqueVRegDef(Subreg);
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@LU-JOHN LU-JOHN Nov 10, 2025

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Since this is operating on SSA form, getVRegDef is better. Also, check if return value is null.

SubRegIsConst[ArrayIdx] = getConstValDefinedInReg(
*RealDefs[ArrayIdx], Subreg, SubRegValues[ArrayIdx]);
}

for (unsigned I : {0, 1})
if (SubRegIsConst[I] && !SubRegValues[I] &&
MRI.getRegClass(RealDefs[(I + 1) % 2]->getOperand(0).getReg())
->MC->getSizeInBits() *
2 ==
MRI.getRegClass(MI.getOperand(0).getReg())->MC->getSizeInBits())
return RealDefs[(I + 1) % 2];

return nullptr;
}

bool SIInstrInfo::getConstValDefinedInReg(const MachineInstr &MI,
const Register Reg,
int64_t &ImmVal) const {
Expand Down Expand Up @@ -10698,6 +10726,9 @@ bool SIInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
if (!Def)
return false;

if (MachineInstr *RegSequenceDef = pierceThroughRegSequence(*Def))
Def = RegSequenceDef;
Comment on lines +10729 to +10730
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@arsenm arsenm Nov 10, 2025

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You need to know the type / subregister at the def and use point, this doesn't have enough context involved to be correct. getConstValDefinedInReg should probably stick to the trivial cases

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@linuxrocks123 linuxrocks123 Nov 10, 2025

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@arsenm I can confirm that the function getConstValDefinedInReg is not changed by this PR.


// For S_OP that set SCC = DST!=0, do the transformation
//
// s_cmp_lg_* (S_OP ...), 0 => (S_OP ...)
Expand Down
2 changes: 2 additions & 0 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.h
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Expand Up @@ -711,6 +711,8 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
}
}

MachineInstr *pierceThroughRegSequence(const MachineInstr &MI) const;

static bool setsSCCifResultIsNonZero(const MachineInstr &MI) {
switch (MI.getOpcode()) {
case AMDGPU::S_ABSDIFF_I32:
Expand Down
22 changes: 22 additions & 0 deletions llvm/test/CodeGen/AMDGPU/redundant-cmp-reg-sequence.ll
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@@ -0,0 +1,22 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s
define amdgpu_ps i64 @ordertest(i64 inreg %val0) {
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@arsenm arsenm Nov 10, 2025

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What does the MIR look like at this point?

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@linuxrocks123 linuxrocks123 Nov 10, 2025

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@arsenm here is the MIR just prior to peephole-opt:

# *** IR Dump After Machine code sinking (machine-sink) ***:
# Machine code for function ordertest: IsSSA, TracksLiveness
Function Live Ins: $sgpr1 in %1

bb.0 (%ir-block.0):
  liveins: $sgpr1
  %1:sgpr_32 = COPY $sgpr1
  %4:sreg_32 = IMPLICIT_DEF
  %3:sgpr_64 = REG_SEQUENCE killed %4:sreg_32, %subreg.sub0, %1:sgpr_32, %subreg.sub1
  %6:sreg_32 = COPY %3.sub1:sgpr_64
  %7:sreg_32 = S_MOV_B32 2
  %8:sreg_32 = S_LSHR_B32 killed %6:sreg_32, killed %7:sreg_32, implicit-def dead $scc
  %9:sreg_32 = S_MOV_B32 0
  %10:sreg_64 = REG_SEQUENCE killed %8:sreg_32, %subreg.sub0, %9:sreg_32, %subreg.sub1
  %11:sreg_64 = S_MOV_B64 0
  S_CMP_LG_U64 %10:sreg_64, killed %11:sreg_64, implicit-def $scc
  %38:sreg_64_xexec = S_CSELECT_B64 -1, 0, implicit $scc
  %13:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %38:sreg_64_xexec, implicit $exec
  %15:vreg_64 = REG_SEQUENCE %13:vgpr_32, %subreg.sub0, %9:sreg_32, %subreg.sub1
  %32:vreg_64 = V_LSHRREV_B64_e64 %13:vgpr_32, %10:sreg_64, implicit $exec
  %25:vgpr_32 = COPY %15.sub0:vreg_64
  %36:vgpr_32 = COPY %32.sub0:vreg_64
  %27:vgpr_32 = COPY %15.sub1:vreg_64
  %37:vgpr_32 = COPY %32.sub1:vreg_64
  %33:vgpr_32 = V_XOR_B32_e64 %25:vgpr_32, %36:vgpr_32, implicit $exec
  %34:vgpr_32 = V_XOR_B32_e64 %27:vgpr_32, %37:vgpr_32, implicit $exec
  %31:vreg_64 = REG_SEQUENCE %33:vgpr_32, %subreg.sub0, %34:vgpr_32, %subreg.sub1
  %35:vgpr_32 = COPY %31.sub0:vreg_64
  %22:sreg_32_xm0 = V_READFIRSTLANE_B32 %35:vgpr_32, implicit $exec
  %24:sreg_32 = S_MOV_B32 %9:sreg_32
  $sgpr0 = COPY %22:sreg_32_xm0
  $sgpr1 = COPY %24:sreg_32
  SI_RETURN_TO_EPILOG $sgpr0, $sgpr1

# End machine code for function ordertest.

; CHECK-LABEL: ordertest:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_lshr_b32 s0, s1, 2
; CHECK-NEXT: s_cselect_b64 s[2:3], -1, 0
; CHECK-NEXT: s_mov_b32 s1, 0
; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[2:3]
; CHECK-NEXT: v_lshrrev_b64 v[0:1], v2, s[0:1]
; CHECK-NEXT: v_xor_b32_e32 v0, v2, v0
; CHECK-NEXT: v_readfirstlane_b32 s0, v0
; CHECK-NEXT: ; return to shader part epilog
%shl = lshr i64 %val0, 34
%result = and i64 %shl, 4294967295
%cmp = icmp ne i64 %result, 0
%zext = zext i1 %cmp to i64
%param0 = lshr i64 %shl, %zext
%param = and i64 %param0, 4294967295
%xory = xor i64 %zext, %param
ret i64 %xory
}
4 changes: 0 additions & 4 deletions llvm/test/CodeGen/AMDGPU/s_cmp_0.ll
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Expand Up @@ -403,8 +403,6 @@ define amdgpu_ps i32 @bfe_i64(i64 inreg %val0) {
; CHECK: ; %bb.0:
; CHECK-NEXT: s_bfe_i64 s[2:3], s[0:1], 0x80000
; CHECK-NEXT: s_and_b32 s0, s0, 0xff
; CHECK-NEXT: s_mov_b32 s1, 0
; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0
; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0
; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; CHECK-NEXT: v_readfirstlane_b32 s0, v0
Expand Down Expand Up @@ -440,7 +438,6 @@ define amdgpu_ps i32 @bfe_u64(i64 inreg %val0) {
; CHECK: ; %bb.0:
; CHECK-NEXT: s_and_b32 s0, s0, 0xff
; CHECK-NEXT: s_mov_b32 s1, 0
; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0
; CHECK-NEXT: ;;#ASMSTART
; CHECK-NEXT: ; use s[0:1]
; CHECK-NEXT: ;;#ASMEND
Expand Down Expand Up @@ -522,7 +519,6 @@ define amdgpu_ps i32 @bcnt164(i64 inreg %val0) {
; CHECK: ; %bb.0:
; CHECK-NEXT: s_bcnt1_i32_b64 s0, s[0:1]
; CHECK-NEXT: s_mov_b32 s1, 0
; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0
; CHECK-NEXT: ;;#ASMSTART
; CHECK-NEXT: ; use s[0:1]
; CHECK-NEXT: ;;#ASMEND
Expand Down
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