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AMDGPU: Replace some uses of getOpRegClass with getRegClass #167447

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Merged
merged 1 commit into from
Nov 11, 2025
Merged

AMDGPU: Replace some uses of getOpRegClass with getRegClass #167447

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8 changes: 5 additions & 3 deletions llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -17367,12 +17367,14 @@ void SITargetLowering::AddMemOpInit(MachineInstr &MI) const {
// Abandon attempt if the dst size isn't large enough
// - this is in fact an error but this is picked up elsewhere and
// reported correctly.
uint32_t DstSize =
TRI.getRegSizeInBits(*TII->getOpRegClass(MI, DstIdx)) / 32;
const TargetRegisterClass *DstRC = TII->getRegClass(MI.getDesc(), DstIdx);

uint32_t DstSize = TRI.getRegSizeInBits(*DstRC) / 32;
if (DstSize < InitIdx)
return;
} else if (TII->isMUBUF(MI) && AMDGPU::getMUBUFTfe(MI.getOpcode())) {
InitIdx = TRI.getRegSizeInBits(*TII->getOpRegClass(MI, DstIdx)) / 32;
const TargetRegisterClass *DstRC = TII->getRegClass(MI.getDesc(), DstIdx);
InitIdx = TRI.getRegSizeInBits(*DstRC) / 32;
} else {
return;
}
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
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Expand Up @@ -3046,7 +3046,7 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
if (!IsMUBUF && !MFI->isBottomOfStack()) {
// Convert to a swizzled stack address by scaling by the wave size.
// In an entry function/kernel the offset is already swizzled.
bool IsSALU = isSGPRClass(TII->getOpRegClass(*MI, FIOperandNum));
bool IsSALU = isSGPRClass(TII->getRegClass(MI->getDesc(), FIOperandNum));
bool LiveSCC = RS->isRegUsed(AMDGPU::SCC) &&
!MI->definesRegister(AMDGPU::SCC, /*TRI=*/nullptr);
const TargetRegisterClass *RC = IsSALU && !LiveSCC
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