[WebAssembly] Lower ANY_EXTEND_VECTOR_INREG #167529
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Treat it in the same manner of zero_extend_vector_inreg and generate an extend_low_u if possible. This is to try an prevent expensive shuffles from being generated instead.
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@llvm/pr-subscribers-backend-webassembly Author: Sam Parker (sparker-arm) ChangesTreat it in the same manner of zero_extend_vector_inreg and generate an extend_low_u if possible. This is to try an prevent expensive shuffles from being generated instead. Full diff: https://github.com/llvm/llvm-project/pull/167529.diff 3 Files Affected:
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
index fc6c2903471a8..97f91b1b72165 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -319,6 +319,7 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
// Support vector extending
for (auto T : MVT::integer_fixedlen_vector_valuetypes()) {
+ setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, T, Custom);
setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, T, Custom);
setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, T, Custom);
}
@@ -1705,6 +1706,7 @@ SDValue WebAssemblyTargetLowering::LowerOperation(SDValue Op,
return LowerSIGN_EXTEND_INREG(Op, DAG);
case ISD::ZERO_EXTEND_VECTOR_INREG:
case ISD::SIGN_EXTEND_VECTOR_INREG:
+ case ISD::ANY_EXTEND_VECTOR_INREG:
return LowerEXTEND_VECTOR_INREG(Op, DAG);
case ISD::BUILD_VECTOR:
return LowerBUILD_VECTOR(Op, DAG);
@@ -2299,6 +2301,9 @@ WebAssemblyTargetLowering::LowerEXTEND_VECTOR_INREG(SDValue Op,
unsigned Ext;
switch (Op.getOpcode()) {
+ default:
+ llvm_unreachable("unexpected opcode");
+ case ISD::ANY_EXTEND_VECTOR_INREG:
case ISD::ZERO_EXTEND_VECTOR_INREG:
Ext = WebAssemblyISD::EXTEND_LOW_U;
break;
diff --git a/llvm/test/CodeGen/WebAssembly/simd-arith.ll b/llvm/test/CodeGen/WebAssembly/simd-arith.ll
index d698fad745dfb..db4f3e16084f2 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-arith.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-arith.ll
@@ -1997,10 +1997,10 @@ define void @avgr_undef_shuffle_lanes(ptr %res, <8 x i8> %a, <8 x i8> %b, <8 x i
; SIMD128: .functype avgr_undef_shuffle_lanes (i32, v128, v128, v128, v128) -> ()
; SIMD128-NEXT: # %bb.0:
; SIMD128-NEXT: i8x16.avgr_u $push1=, $1, $2
-; SIMD128-NEXT: i8x16.shuffle $push12=, $pop1, $4, 0, 0, 1, 0, 2, 0, 3, 0, 4, 0, 5, 0, 6, 0, 7, 0
+; SIMD128-NEXT: i16x8.extend_low_i8x16_u $push12=, $pop1
; SIMD128-NEXT: local.tee $push11=, $2=, $pop12
; SIMD128-NEXT: i8x16.avgr_u $push0=, $3, $4
-; SIMD128-NEXT: i8x16.shuffle $push10=, $pop0, $4, 0, 0, 1, 0, 2, 0, 3, 0, 4, 0, 5, 0, 6, 0, 7, 0
+; SIMD128-NEXT: i16x8.extend_low_i8x16_u $push10=, $pop0
; SIMD128-NEXT: local.tee $push9=, $4=, $pop10
; SIMD128-NEXT: i8x16.shuffle $push4=, $pop11, $pop9, 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23
; SIMD128-NEXT: v128.const $push8=, 255, 255, 255, 255, 255, 255, 255, 255
@@ -2016,10 +2016,10 @@ define void @avgr_undef_shuffle_lanes(ptr %res, <8 x i8> %a, <8 x i8> %b, <8 x i
; SIMD128-FAST: .functype avgr_undef_shuffle_lanes (i32, v128, v128, v128, v128) -> ()
; SIMD128-FAST-NEXT: # %bb.0:
; SIMD128-FAST-NEXT: i8x16.avgr_u $push1=, $1, $2
-; SIMD128-FAST-NEXT: i8x16.shuffle $push12=, $pop1, $4, 0, 0, 1, 0, 2, 0, 3, 0, 4, 0, 5, 0, 6, 0, 7, 0
+; SIMD128-FAST-NEXT: i16x8.extend_low_i8x16_u $push12=, $pop1
; SIMD128-FAST-NEXT: local.tee $push11=, $2=, $pop12
; SIMD128-FAST-NEXT: i8x16.avgr_u $push0=, $3, $4
-; SIMD128-FAST-NEXT: i8x16.shuffle $push10=, $pop0, $4, 0, 0, 1, 0, 2, 0, 3, 0, 4, 0, 5, 0, 6, 0, 7, 0
+; SIMD128-FAST-NEXT: i16x8.extend_low_i8x16_u $push10=, $pop0
; SIMD128-FAST-NEXT: local.tee $push9=, $4=, $pop10
; SIMD128-FAST-NEXT: i8x16.shuffle $push4=, $pop11, $pop9, 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23
; SIMD128-FAST-NEXT: v128.const $push8=, 255, 255, 255, 255, 255, 255, 255, 255
diff --git a/llvm/test/CodeGen/WebAssembly/simd-vecreduce-bool.ll b/llvm/test/CodeGen/WebAssembly/simd-vecreduce-bool.ll
index f7143711394fa..70c6baf2be005 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-vecreduce-bool.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-vecreduce-bool.ll
@@ -276,7 +276,7 @@ define i1 @test_any_v8i8(<8 x i8> %x) {
; CHECK-LABEL: test_any_v8i8:
; CHECK: .functype test_any_v8i8 (v128) -> (i32)
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: i8x16.shuffle $push0=, $0, $0, 0, 0, 1, 0, 2, 0, 3, 0, 4, 0, 5, 0, 6, 0, 7, 0
+; CHECK-NEXT: i16x8.extend_low_i8x16_u $push0=, $0
; CHECK-NEXT: i32.const $push1=, 15
; CHECK-NEXT: i16x8.shl $push2=, $pop0, $pop1
; CHECK-NEXT: i32.const $push5=, 15
@@ -292,7 +292,7 @@ define i1 @test_all_v8i8(<8 x i8> %x) {
; CHECK-LABEL: test_all_v8i8:
; CHECK: .functype test_all_v8i8 (v128) -> (i32)
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: i8x16.shuffle $push0=, $0, $0, 0, 0, 1, 0, 2, 0, 3, 0, 4, 0, 5, 0, 6, 0, 7, 0
+; CHECK-NEXT: i16x8.extend_low_i8x16_u $push0=, $0
; CHECK-NEXT: i32.const $push1=, 15
; CHECK-NEXT: i16x8.shl $push2=, $pop0, $pop1
; CHECK-NEXT: i32.const $push5=, 15
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/129/builds/33566 Here is the relevant piece of the build log for the reference |
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Treat it in the same manner of zero_extend_vector_inreg and generate an extend_low_u if possible. This is to try an prevent expensive shuffles from being generated instead.