[CodeGen] Use MCRegUnit in more places (NFC) #167578
Merged
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Member
|
@llvm/pr-subscribers-llvm-mc @llvm/pr-subscribers-llvm-regalloc Author: Sergei Barannikov (s-barannikov) ChangesFull diff: https://github.com/llvm/llvm-project/pull/167578.diff 14 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/LiveIntervals.h b/llvm/include/llvm/CodeGen/LiveIntervals.h
index c252f9d99f2af..32027766e7093 100644
--- a/llvm/include/llvm/CodeGen/LiveIntervals.h
+++ b/llvm/include/llvm/CodeGen/LiveIntervals.h
@@ -412,7 +412,7 @@ class LiveIntervals {
/// Return the live range for register unit \p Unit. It will be computed if
/// it doesn't exist.
- LiveRange &getRegUnit(unsigned Unit) {
+ LiveRange &getRegUnit(MCRegUnit Unit) {
LiveRange *LR = RegUnitRanges[Unit];
if (!LR) {
// Compute missing ranges on demand.
@@ -425,15 +425,15 @@ class LiveIntervals {
/// Return the live range for register unit \p Unit if it has already been
/// computed, or nullptr if it hasn't been computed yet.
- LiveRange *getCachedRegUnit(unsigned Unit) { return RegUnitRanges[Unit]; }
+ LiveRange *getCachedRegUnit(MCRegUnit Unit) { return RegUnitRanges[Unit]; }
- const LiveRange *getCachedRegUnit(unsigned Unit) const {
+ const LiveRange *getCachedRegUnit(MCRegUnit Unit) const {
return RegUnitRanges[Unit];
}
/// Remove computed live range for register unit \p Unit. Subsequent uses
/// should rely on on-demand recomputation.
- void removeRegUnit(unsigned Unit) {
+ void removeRegUnit(MCRegUnit Unit) {
delete RegUnitRanges[Unit];
RegUnitRanges[Unit] = nullptr;
}
@@ -489,7 +489,7 @@ class LiveIntervals {
void dumpInstrs() const;
void computeLiveInRegUnits();
- LLVM_ABI void computeRegUnitRange(LiveRange &, unsigned Unit);
+ LLVM_ABI void computeRegUnitRange(LiveRange &, MCRegUnit Unit);
LLVM_ABI bool computeVirtRegInterval(LiveInterval &);
using ShrinkToUsesWorkList = SmallVector<std::pair<SlotIndex, VNInfo *>, 16>;
diff --git a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
index 27b30bd5929ff..6982dae4718d1 100644
--- a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
@@ -982,7 +982,7 @@ class MachineRegisterInfo {
/// root registers, the root register and all super registers are reserved.
/// This currently iterates the register hierarchy and may be slower than
/// expected.
- LLVM_ABI bool isReservedRegUnit(unsigned Unit) const;
+ LLVM_ABI bool isReservedRegUnit(MCRegUnit Unit) const;
/// isAllocatable - Returns true when PhysReg belongs to an allocatable
/// register class and it hasn't been reserved.
diff --git a/llvm/include/llvm/CodeGen/ReachingDefAnalysis.h b/llvm/include/llvm/CodeGen/ReachingDefAnalysis.h
index d987a5cf1c3df..2893e5ce6647e 100644
--- a/llvm/include/llvm/CodeGen/ReachingDefAnalysis.h
+++ b/llvm/include/llvm/CodeGen/ReachingDefAnalysis.h
@@ -77,23 +77,23 @@ class MBBReachingDefsInfo {
AllReachingDefs[MBBNumber].resize(NumRegUnits);
}
- void append(unsigned MBBNumber, unsigned Unit, int Def) {
+ void append(unsigned MBBNumber, MCRegUnit Unit, int Def) {
AllReachingDefs[MBBNumber][Unit].push_back(Def);
}
- void prepend(unsigned MBBNumber, unsigned Unit, int Def) {
+ void prepend(unsigned MBBNumber, MCRegUnit Unit, int Def) {
auto &Defs = AllReachingDefs[MBBNumber][Unit];
Defs.insert(Defs.begin(), Def);
}
- void replaceFront(unsigned MBBNumber, unsigned Unit, int Def) {
+ void replaceFront(unsigned MBBNumber, MCRegUnit Unit, int Def) {
assert(!AllReachingDefs[MBBNumber][Unit].empty());
*AllReachingDefs[MBBNumber][Unit].begin() = Def;
}
void clear() { AllReachingDefs.clear(); }
- ArrayRef<ReachingDef> defs(unsigned MBBNumber, unsigned Unit) const {
+ ArrayRef<ReachingDef> defs(unsigned MBBNumber, MCRegUnit Unit) const {
if (AllReachingDefs[MBBNumber].empty())
// Block IDs are not necessarily dense.
return ArrayRef<ReachingDef>();
diff --git a/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h b/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
index ab0d7e334df44..059a3444c609c 100644
--- a/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
+++ b/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
@@ -77,9 +77,9 @@ namespace llvm {
struct PhysRegSUOper {
SUnit *SU;
int OpIdx;
- unsigned RegUnit;
+ MCRegUnit RegUnit;
- PhysRegSUOper(SUnit *su, int op, unsigned R)
+ PhysRegSUOper(SUnit *su, int op, MCRegUnit R)
: SU(su), OpIdx(op), RegUnit(R) {}
unsigned getSparseSetIndex() const { return RegUnit; }
diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
index f031353422e40..992d5a50a8bbf 100644
--- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
@@ -1446,7 +1446,7 @@ LLVM_ABI Printable printReg(Register Reg,
/// fp0~st7 - Dual roots.
///
/// Usage: OS << printRegUnit(Unit, TRI) << '\n';
-LLVM_ABI Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI);
+LLVM_ABI Printable printRegUnit(MCRegUnit Unit, const TargetRegisterInfo *TRI);
/// Create Printable object to print virtual registers and physical
/// registers on a \ref raw_ostream.
diff --git a/llvm/include/llvm/MC/MCRegisterInfo.h b/llvm/include/llvm/MC/MCRegisterInfo.h
index f611edd715398..e6dbb38dfee67 100644
--- a/llvm/include/llvm/MC/MCRegisterInfo.h
+++ b/llvm/include/llvm/MC/MCRegisterInfo.h
@@ -687,7 +687,7 @@ class MCRegUnitMaskIterator {
}
/// Returns a (RegUnit, LaneMask) pair.
- std::pair<unsigned,LaneBitmask> operator*() const {
+ std::pair<MCRegUnit, LaneBitmask> operator*() const {
return std::make_pair(*RUIter, *MaskListIter);
}
@@ -719,7 +719,7 @@ class MCRegUnitRootIterator {
public:
MCRegUnitRootIterator() = default;
- MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) {
+ MCRegUnitRootIterator(MCRegUnit RegUnit, const MCRegisterInfo *MCRI) {
assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit");
Reg0 = MCRI->RegUnitRoots[RegUnit][0];
Reg1 = MCRI->RegUnitRoots[RegUnit][1];
diff --git a/llvm/lib/CodeGen/EarlyIfConversion.cpp b/llvm/lib/CodeGen/EarlyIfConversion.cpp
index da0987c3b50bb..55caa6e8a8f95 100644
--- a/llvm/lib/CodeGen/EarlyIfConversion.cpp
+++ b/llvm/lib/CodeGen/EarlyIfConversion.cpp
@@ -134,7 +134,7 @@ class SSAIfConv {
BitVector ClobberedRegUnits;
// Scratch pad for findInsertionPoint.
- SparseSet<unsigned> LiveRegUnits;
+ SparseSet<MCRegUnit> LiveRegUnits;
/// Insertion point in Head for speculatively executed instructions form TBB
/// and FBB.
@@ -421,7 +421,7 @@ bool SSAIfConv::findInsertionPoint() {
if (!LiveRegUnits.empty()) {
LLVM_DEBUG({
dbgs() << "Would clobber";
- for (unsigned LRU : LiveRegUnits)
+ for (MCRegUnit LRU : LiveRegUnits)
dbgs() << ' ' << printRegUnit(LRU, TRI);
dbgs() << " live before " << *I;
});
diff --git a/llvm/lib/CodeGen/LiveIntervals.cpp b/llvm/lib/CodeGen/LiveIntervals.cpp
index d2f2c3ef33c9c..27c5addffa4ab 100644
--- a/llvm/lib/CodeGen/LiveIntervals.cpp
+++ b/llvm/lib/CodeGen/LiveIntervals.cpp
@@ -305,7 +305,7 @@ void LiveIntervals::computeRegMasks() {
/// Compute the live range of a register unit, based on the uses and defs of
/// aliasing registers. The range should be empty, or contain only dead
/// phi-defs from ABI blocks.
-void LiveIntervals::computeRegUnitRange(LiveRange &LR, unsigned Unit) {
+void LiveIntervals::computeRegUnitRange(LiveRange &LR, MCRegUnit Unit) {
assert(LICalc && "LICalc not initialized.");
LICalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
@@ -354,7 +354,7 @@ void LiveIntervals::computeLiveInRegUnits() {
LLVM_DEBUG(dbgs() << "Computing live-in reg-units in ABI blocks.\n");
// Keep track of the live range sets allocated.
- SmallVector<unsigned, 8> NewRanges;
+ SmallVector<MCRegUnit, 8> NewRanges;
// Check all basic blocks for live-ins.
for (const MachineBasicBlock &MBB : *MF) {
@@ -383,7 +383,7 @@ void LiveIntervals::computeLiveInRegUnits() {
LLVM_DEBUG(dbgs() << "Created " << NewRanges.size() << " new intervals.\n");
// Compute the 'normal' part of the ranges.
- for (unsigned Unit : NewRanges)
+ for (MCRegUnit Unit : NewRanges)
computeRegUnitRange(*RegUnitRanges[Unit], Unit);
}
@@ -1042,7 +1042,7 @@ class LiveIntervals::HMEditor {
// physregs, even those that aren't needed for regalloc, in order to update
// kill flags. This is wasteful. Eventually, LiveVariables will strip all kill
// flags, and postRA passes will use a live register utility instead.
- LiveRange *getRegUnitLI(unsigned Unit) {
+ LiveRange *getRegUnitLI(MCRegUnit Unit) {
if (UpdateFlags && !MRI.isReservedRegUnit(Unit))
return &LIS.getRegUnit(Unit);
return LIS.getCachedRegUnit(Unit);
diff --git a/llvm/lib/CodeGen/LiveRegMatrix.cpp b/llvm/lib/CodeGen/LiveRegMatrix.cpp
index cfda262aac82d..e3ee8dc325933 100644
--- a/llvm/lib/CodeGen/LiveRegMatrix.cpp
+++ b/llvm/lib/CodeGen/LiveRegMatrix.cpp
@@ -89,7 +89,7 @@ static bool foreachUnit(const TargetRegisterInfo *TRI,
Callable Func) {
if (VRegInterval.hasSubRanges()) {
for (MCRegUnitMaskIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
- unsigned Unit = (*Units).first;
+ MCRegUnit Unit = (*Units).first;
LaneBitmask Mask = (*Units).second;
for (const LiveInterval::SubRange &S : VRegInterval.subranges()) {
if ((S.LaneMask & Mask).any()) {
@@ -115,7 +115,7 @@ void LiveRegMatrix::assign(const LiveInterval &VirtReg, MCRegister PhysReg) {
VRM->assignVirt2Phys(VirtReg.reg(), PhysReg);
foreachUnit(
- TRI, VirtReg, PhysReg, [&](unsigned Unit, const LiveRange &Range) {
+ TRI, VirtReg, PhysReg, [&](MCRegUnit Unit, const LiveRange &Range) {
LLVM_DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI) << ' ' << Range);
Matrix[Unit].unify(VirtReg, Range);
return false;
@@ -132,7 +132,7 @@ void LiveRegMatrix::unassign(const LiveInterval &VirtReg) {
VRM->clearVirt(VirtReg.reg());
foreachUnit(TRI, VirtReg, PhysReg,
- [&](unsigned Unit, const LiveRange &Range) {
+ [&](MCRegUnit Unit, const LiveRange &Range) {
LLVM_DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI));
Matrix[Unit].extract(VirtReg, Range);
return false;
@@ -175,11 +175,11 @@ bool LiveRegMatrix::checkRegUnitInterference(const LiveInterval &VirtReg,
return false;
CoalescerPair CP(VirtReg.reg(), PhysReg, *TRI);
- bool Result = foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit,
- const LiveRange &Range) {
- const LiveRange &UnitRange = LIS->getRegUnit(Unit);
- return Range.overlaps(UnitRange, CP, *LIS->getSlotIndexes());
- });
+ bool Result = foreachUnit(
+ TRI, VirtReg, PhysReg, [&](MCRegUnit Unit, const LiveRange &Range) {
+ const LiveRange &UnitRange = LIS->getRegUnit(Unit);
+ return Range.overlaps(UnitRange, CP, *LIS->getSlotIndexes());
+ });
return Result;
}
diff --git a/llvm/lib/CodeGen/MachineCopyPropagation.cpp b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
index ea08365810a29..27dc1db309c6a 100644
--- a/llvm/lib/CodeGen/MachineCopyPropagation.cpp
+++ b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
@@ -137,7 +137,7 @@ class CopyTracker {
PreservedRegUnits.resize(TRI.getNumRegUnits());
for (unsigned SafeReg = 0, E = TRI.getNumRegs(); SafeReg < E; ++SafeReg)
if (!RegMaskOp.clobbersPhysReg(SafeReg))
- for (auto SafeUnit : TRI.regunits(SafeReg))
+ for (MCRegUnit SafeUnit : TRI.regunits(SafeReg))
PreservedRegUnits.set(SafeUnit);
return PreservedRegUnits;
@@ -1005,7 +1005,7 @@ void MachineCopyPropagation::ForwardCopyPropagateBlock(MachineBasicBlock &MBB) {
// Invalidate all entries in the copy map which are not preserved by
// this register mask.
bool MIRefedinCopyInfo = false;
- for (unsigned RegUnit : TRI->regunits(Reg)) {
+ for (MCRegUnit RegUnit : TRI->regunits(Reg)) {
if (!PreservedRegUnits.test(RegUnit))
Tracker.clobberRegUnit(RegUnit, *TRI, *TII, UseCopyInstr);
else {
diff --git a/llvm/lib/CodeGen/MachineRegisterInfo.cpp b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
index ae284f3ae2929..094315b3903ea 100644
--- a/llvm/lib/CodeGen/MachineRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
@@ -665,7 +665,7 @@ void MachineRegisterInfo::setCalleeSavedRegs(ArrayRef<MCPhysReg> CSRs) {
IsUpdatedCSRsInitialized = true;
}
-bool MachineRegisterInfo::isReservedRegUnit(unsigned Unit) const {
+bool MachineRegisterInfo::isReservedRegUnit(MCRegUnit Unit) const {
const TargetRegisterInfo *TRI = getTargetRegisterInfo();
for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {
if (all_of(TRI->superregs_inclusive(*Root),
diff --git a/llvm/lib/CodeGen/RDFRegisters.cpp b/llvm/lib/CodeGen/RDFRegisters.cpp
index b8d54cadc07f6..1400699a607ff 100644
--- a/llvm/lib/CodeGen/RDFRegisters.cpp
+++ b/llvm/lib/CodeGen/RDFRegisters.cpp
@@ -58,7 +58,7 @@ PhysicalRegisterInfo::PhysicalRegisterInfo(const TargetRegisterInfo &tri,
UnitInfos[U].Reg = F;
} else {
for (MCRegUnitMaskIterator I(F, &TRI); I.isValid(); ++I) {
- std::pair<uint32_t, LaneBitmask> P = *I;
+ std::pair<MCRegUnit, LaneBitmask> P = *I;
UnitInfo &UI = UnitInfos[P.first];
UI.Reg = F;
UI.Mask = P.second;
@@ -281,9 +281,9 @@ bool RegisterAggr::hasAliasOf(RegisterRef RR) const {
return Units.anyCommon(PRI.getMaskUnits(RR.Reg));
for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) {
- std::pair<uint32_t, LaneBitmask> P = *U;
- if ((P.second & RR.Mask).any())
- if (Units.test(P.first))
+ auto [Unit, LaneMask] = *U;
+ if ((LaneMask & RR.Mask).any())
+ if (Units.test(Unit))
return true;
}
return false;
@@ -296,9 +296,9 @@ bool RegisterAggr::hasCoverOf(RegisterRef RR) const {
}
for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) {
- std::pair<uint32_t, LaneBitmask> P = *U;
- if ((P.second & RR.Mask).any())
- if (!Units.test(P.first))
+ auto [Unit, LaneMask] = *U;
+ if ((LaneMask & RR.Mask).any())
+ if (!Units.test(Unit))
return false;
}
return true;
@@ -311,9 +311,9 @@ RegisterAggr &RegisterAggr::insert(RegisterRef RR) {
}
for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) {
- std::pair<uint32_t, LaneBitmask> P = *U;
- if ((P.second & RR.Mask).any())
- Units.set(P.first);
+ auto [Unit, LaneMask] = *U;
+ if ((LaneMask & RR.Mask).any())
+ Units.set(Unit);
}
return *this;
}
@@ -384,9 +384,9 @@ RegisterRef RegisterAggr::makeRegRef() const {
LaneBitmask M;
for (MCRegUnitMaskIterator I(F, &PRI.getTRI()); I.isValid(); ++I) {
- std::pair<uint32_t, LaneBitmask> P = *I;
- if (Units.test(P.first))
- M |= P.second;
+ auto [Unit, LaneMask] = *I;
+ if (Units.test(Unit))
+ M |= LaneMask;
}
return RegisterRef(F, M);
}
diff --git a/llvm/lib/CodeGen/TargetRegisterInfo.cpp b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
index 971f822fa6c53..a5c81afc57a80 100644
--- a/llvm/lib/CodeGen/TargetRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
@@ -133,7 +133,7 @@ Printable llvm::printReg(Register Reg, const TargetRegisterInfo *TRI,
});
}
-Printable llvm::printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
+Printable llvm::printRegUnit(MCRegUnit Unit, const TargetRegisterInfo *TRI) {
return Printable([Unit, TRI](raw_ostream &OS) {
// Generic printout when TRI is missing.
if (!TRI) {
diff --git a/llvm/lib/MC/MCRegisterInfo.cpp b/llvm/lib/MC/MCRegisterInfo.cpp
index ba9ef00f9f0d8..7fd92bf974b95 100644
--- a/llvm/lib/MC/MCRegisterInfo.cpp
+++ b/llvm/lib/MC/MCRegisterInfo.cpp
@@ -221,7 +221,7 @@ bool MCRegisterInfo::regsOverlap(MCRegister RegA, MCRegister RegB) const {
return false;
}
-bool MCRegisterInfo::isArtificialRegUnit(unsigned Unit) const {
+bool MCRegisterInfo::isArtificialRegUnit(MCRegUnit Unit) const {
for (MCRegUnitRootIterator Root(Unit, this); Root.isValid(); ++Root)
if (isArtificial(*Root))
return true;
|
arsenm
approved these changes
Nov 11, 2025
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
4 participants
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
No description provided.