[RISCV] Remove implicit conversions of MCRegister to unsigned. NFC #167588
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Rename RegNum to Reg.
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@llvm/pr-subscribers-backend-risc-v Author: Craig Topper (topperc) ChangesRename RegNum to Reg. Full diff: https://github.com/llvm/llvm-project/pull/167588.diff 3 Files Affected:
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index edde7ac487da3..10588b9739188 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -352,7 +352,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
} Kind;
struct RegOp {
- MCRegister RegNum;
+ MCRegister Reg;
bool IsGPRAsFPR;
};
@@ -461,20 +461,18 @@ struct RISCVOperand final : public MCParsedAsmOperand {
bool isReg() const override { return Kind == KindTy::Register; }
bool isExpr() const { return Kind == KindTy::Expression; }
bool isV0Reg() const {
- return Kind == KindTy::Register && Reg.RegNum == RISCV::V0;
+ return Kind == KindTy::Register && Reg.Reg == RISCV::V0;
}
bool isAnyReg() const {
return Kind == KindTy::Register &&
- (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg.RegNum) ||
- RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(Reg.RegNum) ||
- RISCVMCRegisterClasses[RISCV::VRRegClassID].contains(Reg.RegNum));
+ (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg.Reg) ||
+ RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(Reg.Reg) ||
+ RISCVMCRegisterClasses[RISCV::VRRegClassID].contains(Reg.Reg));
}
bool isAnyRegC() const {
return Kind == KindTy::Register &&
- (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(
- Reg.RegNum) ||
- RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(
- Reg.RegNum));
+ (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(Reg.Reg) ||
+ RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(Reg.Reg));
}
bool isImm() const override { return isExpr(); }
bool isMem() const override { return false; }
@@ -488,35 +486,33 @@ struct RISCVOperand final : public MCParsedAsmOperand {
bool isGPR() const {
return Kind == KindTy::Register &&
- RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg.RegNum);
+ RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg.Reg);
}
bool isGPRPair() const {
return Kind == KindTy::Register &&
- RISCVMCRegisterClasses[RISCV::GPRPairRegClassID].contains(
- Reg.RegNum);
+ RISCVMCRegisterClasses[RISCV::GPRPairRegClassID].contains(Reg.Reg);
}
bool isGPRPairC() const {
return Kind == KindTy::Register &&
- RISCVMCRegisterClasses[RISCV::GPRPairCRegClassID].contains(
- Reg.RegNum);
+ RISCVMCRegisterClasses[RISCV::GPRPairCRegClassID].contains(Reg.Reg);
}
bool isGPRPairNoX0() const {
return Kind == KindTy::Register &&
RISCVMCRegisterClasses[RISCV::GPRPairNoX0RegClassID].contains(
- Reg.RegNum);
+ Reg.Reg);
}
bool isGPRF16() const {
return Kind == KindTy::Register &&
- RISCVMCRegisterClasses[RISCV::GPRF16RegClassID].contains(Reg.RegNum);
+ RISCVMCRegisterClasses[RISCV::GPRF16RegClassID].contains(Reg.Reg);
}
bool isGPRF32() const {
return Kind == KindTy::Register &&
- RISCVMCRegisterClasses[RISCV::GPRF32RegClassID].contains(Reg.RegNum);
+ RISCVMCRegisterClasses[RISCV::GPRF32RegClassID].contains(Reg.Reg);
}
bool isGPRAsFPR() const { return isGPR() && Reg.IsGPRAsFPR; }
@@ -991,7 +987,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
MCRegister getReg() const override {
assert(Kind == KindTy::Register && "Invalid type access!");
- return Reg.RegNum;
+ return Reg.Reg;
}
StringRef getSysReg() const {
@@ -1047,7 +1043,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
OS << "<fpimm: " << FPImm.Val << ">";
break;
case KindTy::Register:
- OS << "<reg: " << RegName(Reg.RegNum) << " (" << Reg.RegNum
+ OS << "<reg: " << RegName(Reg.Reg) << " (" << Reg.Reg.id()
<< (Reg.IsGPRAsFPR ? ") GPRasFPR>" : ")>");
break;
case KindTy::Token:
@@ -1099,7 +1095,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
static std::unique_ptr<RISCVOperand>
createReg(MCRegister Reg, SMLoc S, SMLoc E, bool IsGPRAsFPR = false) {
auto Op = std::make_unique<RISCVOperand>(KindTy::Register);
- Op->Reg.RegNum = Reg;
+ Op->Reg.Reg = Reg;
Op->Reg.IsGPRAsFPR = IsGPRAsFPR;
Op->StartLoc = S;
Op->EndLoc = E;
@@ -1335,28 +1331,28 @@ unsigned RISCVAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
bool IsRegVR = RISCVMCRegisterClasses[RISCV::VRRegClassID].contains(Reg);
if (IsRegFPR64 && Kind == MCK_FPR128) {
- Op.Reg.RegNum = convertFPR64ToFPR128(Reg);
+ Op.Reg.Reg = convertFPR64ToFPR128(Reg);
return Match_Success;
}
// As the parser couldn't differentiate an FPR32 from an FPR64, coerce the
// register from FPR64 to FPR32 or FPR64C to FPR32C if necessary.
if ((IsRegFPR64 && Kind == MCK_FPR32) ||
(IsRegFPR64C && Kind == MCK_FPR32C)) {
- Op.Reg.RegNum = convertFPR64ToFPR32(Reg);
+ Op.Reg.Reg = convertFPR64ToFPR32(Reg);
return Match_Success;
}
// As the parser couldn't differentiate an FPR16 from an FPR64, coerce the
// register from FPR64 to FPR16 if necessary.
if (IsRegFPR64 && Kind == MCK_FPR16) {
- Op.Reg.RegNum = convertFPR64ToFPR16(Reg);
+ Op.Reg.Reg = convertFPR64ToFPR16(Reg);
return Match_Success;
}
if (Kind == MCK_GPRAsFPR16 && Op.isGPRAsFPR()) {
- Op.Reg.RegNum = Reg - RISCV::X0 + RISCV::X0_H;
+ Op.Reg.Reg = Reg - RISCV::X0 + RISCV::X0_H;
return Match_Success;
}
if (Kind == MCK_GPRAsFPR32 && Op.isGPRAsFPR()) {
- Op.Reg.RegNum = Reg - RISCV::X0 + RISCV::X0_W;
+ Op.Reg.Reg = Reg - RISCV::X0 + RISCV::X0_W;
return Match_Success;
}
@@ -1372,8 +1368,8 @@ unsigned RISCVAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
// As the parser couldn't differentiate an VRM2/VRM4/VRM8 from an VR, coerce
// the register from VR to VRM2/VRM4/VRM8 if necessary.
if (IsRegVR && (Kind == MCK_VRM2 || Kind == MCK_VRM4 || Kind == MCK_VRM8)) {
- Op.Reg.RegNum = convertVRToVRMx(*getContext().getRegisterInfo(), Reg, Kind);
- if (!Op.Reg.RegNum)
+ Op.Reg.Reg = convertVRToVRMx(*getContext().getRegisterInfo(), Reg, Kind);
+ if (!Op.Reg.Reg)
return Match_InvalidOperand;
return Match_Success;
}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index 5b8cfb2100b26..d8dcd963050b5 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -700,7 +700,7 @@ enum RLISTENCODE {
inline unsigned encodeRegList(MCRegister EndReg, bool IsRVE = false) {
assert((!IsRVE || EndReg <= RISCV::X9) && "Invalid Rlist for RV32E");
- switch (EndReg) {
+ switch (EndReg.id()) {
case RISCV::X1:
return RLISTENCODE::RA;
case RISCV::X8:
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
index 5934c91cb4b9a..fd460e457a415 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
@@ -725,7 +725,7 @@ unsigned RISCVMCCodeEmitter::getVMaskReg(const MCInst &MI, unsigned OpNo,
MCOperand MO = MI.getOperand(OpNo);
assert(MO.isReg() && "Expected a register.");
- switch (MO.getReg()) {
+ switch (MO.getReg().id()) {
default:
llvm_unreachable("Invalid mask register.");
case RISCV::V0:
|
arsenm
approved these changes
Nov 11, 2025
lenary
reviewed
Nov 11, 2025
Comment on lines
+1351
to
+1355
| Op.Reg.Reg = Reg - RISCV::X0 + RISCV::X0_H; | ||
| return Match_Success; | ||
| } | ||
| if (Kind == MCK_GPRAsFPR32 && Op.isGPRAsFPR()) { | ||
| Op.Reg.RegNum = Reg - RISCV::X0 + RISCV::X0_W; | ||
| Op.Reg.Reg = Reg - RISCV::X0 + RISCV::X0_W; |
Member
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Aren't these still using the implicit conversion to/from unsigned?
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Subtractions of MCRegister and unsigned are very common so I have a MCRegister::operator-(MCRegister, unsigned) in my working tree right now that's hiding this. I'm considering keeping it and asserting that the right hand side is less than the left hand side.
lenary
reviewed
Nov 11, 2025
lenary
approved these changes
Nov 11, 2025
Collaborator
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/134/builds/29663 Here is the relevant piece of the build log for the reference |
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Rename RegNum to Reg.