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Merged
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Nov 13, 2025
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[ASan][Windows] Add new instruction sizes #167734

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4 changes: 4 additions & 0 deletions compiler-rt/lib/interception/interception_win.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -646,6 +646,7 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
case 0xC033: // 33 C0 : xor eax, eax
case 0xC933: // 33 C9 : xor ecx, ecx
case 0xD233: // 33 D2 : xor edx, edx
case 0xFF33: // 33 FF : xor edi, edi
case 0x9066: // 66 90 : xchg %ax,%ax (Two-byte NOP)
case 0xDB84: // 84 DB : test bl,bl
case 0xC084: // 84 C0 : test al,al
Expand Down Expand Up @@ -764,6 +765,7 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {

switch (0x00FFFFFF & *(u32 *)address) {
case 0x10b70f: // 0f b7 10 : movzx edx, WORD PTR [rax]
case 0x02b70f: // 0f b7 02 : movzx eax, WORD PTR [rdx]
case 0xc00b4d: // 4d 0b c0 : or r8, r8
case 0xc03345: // 45 33 c0 : xor r8d, r8d
case 0xc08548: // 48 85 c0 : test rax, rax
Expand Down Expand Up @@ -799,6 +801,7 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
case 0xc9854d: // 4d 85 c9 : test r9, r9
case 0xc98b4c: // 4c 8b c9 : mov r9, rcx
case 0xd12948: // 48 29 d1 : sub rcx, rdx
case 0xc22b4c: // 4c 2b c2 : sub r8, rdx
case 0xca2b48: // 48 2b ca : sub rcx, rdx
case 0xca3b48: // 48 3b ca : cmp rcx, rdx
case 0xd12b48: // 48 2b d1 : sub rdx, rcx
Expand All @@ -813,6 +816,7 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
case 0xd9f748: // 48 f7 d9 : neg rcx
case 0xc03145: // 45 31 c0 : xor r8d,r8d
case 0xc93145: // 45 31 c9 : xor r9d,r9d
case 0xd23345: // 45 33 d2 : xor r10d, r10d
case 0xdb3345: // 45 33 db : xor r11d, r11d
case 0xc08445: // 45 84 c0 : test r8b,r8b
case 0xd28445: // 45 84 d2 : test r10b,r10b
Expand Down
4 changes: 4 additions & 0 deletions compiler-rt/lib/interception/tests/interception_win_test.cpp
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Expand Up @@ -841,6 +841,7 @@ const struct InstructionSizeData {
{ 1, {0xCC}, 0, "CC : int 3 i.e. registering weak functions)"},
{ 2, {0x31, 0xC0}, 0, "31 C0 : xor eax, eax"},
{ 2, {0x31, 0xC9}, 0, "31 C9 : xor ecx, ecx"},
{ 2, {0x33, 0xFF}, 0, "33 FF : xor edi, edi"},
{ 2, {0x31, 0xD2}, 0, "31 D2 : xor edx, edx"},
{ 2, {0x33, 0xC0}, 0, "33 C0 : xor eax, eax"},
{ 2, {0x33, 0xC9}, 0, "33 C9 : xor ecx, ecx"},
Expand Down Expand Up @@ -895,6 +896,7 @@ const struct InstructionSizeData {
{ 3, {0x0f, 0xb6, 0x11}, 0, "0f b6 11 : movzx edx, BYTE PTR [rcx]"},
{ 3, {0x0f, 0xb6, 0xc2}, 0, "0f b6 c2 : movzx eax, dl"},
{ 3, {0x0f, 0xb6, 0xd2}, 0, "0f b6 d2 : movzx edx, dl"},
{ 3, (0x0f, 0xb7, 0x02), 0, "0f b7 02 : movzx eax, WORD PTR [rdx]"}.
{ 3, {0x0f, 0xb7, 0x10}, 0, "0f b7 10 : movzx edx, WORD PTR [rax]"},
{ 3, {0x0f, 0xbe, 0xd2}, 0, "0f be d2 : movsx edx, dl"},
{ 3, {0x41, 0x8b, 0xc0}, 0, "41 8b c0 : mov eax, r8d"},
Expand All @@ -906,6 +908,7 @@ const struct InstructionSizeData {
{ 3, {0x45, 0x31, 0xc9}, 0, "45 31 c9 : xor r9d,r9d"},
{ 3, {0x45, 0x33, 0xc0}, 0, "45 33 c0 : xor r8d, r8d"},
{ 3, {0x45, 0x33, 0xc9}, 0, "45 33 c9 : xor r9d, r9d"},
{ 3, (0x45, 0x33, 0xd2), 0, "45 33 d2 : xor r10d, r10d"},
{ 3, {0x45, 0x33, 0xdb}, 0, "45 33 db : xor r11d, r11d"},
{ 3, {0x45, 0x84, 0xc0}, 0, "45 84 c0 : test r8b,r8b"},
{ 3, {0x45, 0x84, 0xd2}, 0, "45 84 d2 : test r10b,r10b"},
Expand Down Expand Up @@ -950,6 +953,7 @@ const struct InstructionSizeData {
{ 3, {0x49, 0xff, 0xc5}, 0, "49 ff c5 : inc r13"},
{ 3, {0x49, 0xff, 0xc6}, 0, "49 ff c6 : inc r14"},
{ 3, {0x49, 0xff, 0xc7}, 0, "49 ff c7 : inc r15"},
{ 3, {0x4c, 0x2b, 0xc2}, 0, "4c 2b c2 : sub r8, rdx"},
{ 3, {0x4c, 0x8b, 0xc1}, 0, "4c 8b c1 : mov r8, rcx"},
{ 3, {0x4c, 0x8b, 0xc9}, 0, "4c 8b c9 : mov r9, rcx"},
{ 3, {0x4c, 0x8b, 0xd1}, 0, "4c 8b d1 : mov r10, rcx"},
Expand Down
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