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[AArch64][llvm] Improve writeback reg handling for FEAT_MOPS #167763

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Merged
merged 2 commits into from
Nov 13, 2025
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[AArch64][llvm] Improve writeback reg handling for FEAT_MOPS #167763

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7aa4c56
[AArch64][llvm] Improve writeback reg handling for FEAT_MOPS
jthackray Nov 12, 2025
ed1fdbc
fixup! [AArch64][llvm] Improve writeback reg handling for FEAT_MOPS
jthackray Nov 13, 2025
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44 changes: 16 additions & 28 deletions llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5923,21 +5923,15 @@ bool AArch64AsmParser::validateInstruction(MCInst &Inst, SMLoc &IDLoc,
case AArch64::CPYETWN:
case AArch64::CPYETRN:
case AArch64::CPYETN: {
MCRegister Xd_wb = Inst.getOperand(0).getReg();
MCRegister Xs_wb = Inst.getOperand(1).getReg();
MCRegister Xn_wb = Inst.getOperand(2).getReg();
// Xd_wb == op0, Xs_wb == op1, Xn_wb == op2
MCRegister Xd = Inst.getOperand(3).getReg();
MCRegister Xs = Inst.getOperand(4).getReg();
MCRegister Xn = Inst.getOperand(5).getReg();
if (Xd_wb != Xd)
return Error(Loc[0],
"invalid CPY instruction, Xd_wb and Xd do not match");
if (Xs_wb != Xs)
return Error(Loc[0],
"invalid CPY instruction, Xs_wb and Xs do not match");
if (Xn_wb != Xn)
return Error(Loc[0],
"invalid CPY instruction, Xn_wb and Xn do not match");

assert(Xd == Inst.getOperand(0).getReg() && "Xd_wb and Xd do not match");
assert(Xs == Inst.getOperand(1).getReg() && "Xs_wb and Xs do not match");
assert(Xn == Inst.getOperand(2).getReg() && "Xn_wb and Xn do not match");

if (Xd == Xs)
return Error(Loc[0], "invalid CPY instruction, destination and source"
" registers are the same");
Expand Down Expand Up @@ -5973,17 +5967,14 @@ bool AArch64AsmParser::validateInstruction(MCInst &Inst, SMLoc &IDLoc,
case AArch64::MOPSSETGET:
case AArch64::MOPSSETGEN:
case AArch64::MOPSSETGETN: {
MCRegister Xd_wb = Inst.getOperand(0).getReg();
MCRegister Xn_wb = Inst.getOperand(1).getReg();
// Xd_wb == op0, Xn_wb == op1
MCRegister Xd = Inst.getOperand(2).getReg();
MCRegister Xn = Inst.getOperand(3).getReg();
MCRegister Xm = Inst.getOperand(4).getReg();
if (Xd_wb != Xd)
return Error(Loc[0],
"invalid SET instruction, Xd_wb and Xd do not match");
if (Xn_wb != Xn)
return Error(Loc[0],
"invalid SET instruction, Xn_wb and Xn do not match");

assert(Xd == Inst.getOperand(0).getReg() && "Xd_wb and Xd do not match");
assert(Xn == Inst.getOperand(1).getReg() && "Xn_wb and Xn do not match");

if (Xd == Xn)
return Error(Loc[0], "invalid SET instruction, destination and size"
" registers are the same");
Expand All @@ -6007,16 +5998,13 @@ bool AArch64AsmParser::validateInstruction(MCInst &Inst, SMLoc &IDLoc,
case AArch64::SETGOET:
case AArch64::SETGOEN:
case AArch64::SETGOETN: {
MCRegister Xd_wb = Inst.getOperand(0).getReg();
MCRegister Xn_wb = Inst.getOperand(1).getReg();
// Xd_wb == op0, Xn_wb == op1
MCRegister Xd = Inst.getOperand(2).getReg();
MCRegister Xn = Inst.getOperand(3).getReg();
if (Xd_wb != Xd)
return Error(Loc[0],
"invalid SET instruction, Xd_wb and Xd do not match");
if (Xn_wb != Xn)
return Error(Loc[0],
"invalid SET instruction, Xn_wb and Xn do not match");

assert(Xd == Inst.getOperand(0).getReg() && "Xd_wb and Xd do not match");
assert(Xn == Inst.getOperand(1).getReg() && "Xn_wb and Xn do not match");

if (Xd == Xn)
return Error(Loc[0], "invalid SET instruction, destination and size"
" registers are the same");
Expand Down
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