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[RISCV][llvm] Handle INSERT_VECTOR_ELT, EXTRACT_VECTOR_ELT codegen for zvfbfa #167819

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Merged
merged 1 commit into from
Nov 13, 2025
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[RISCV][llvm] Handle INSERT_VECTOR_ELT, EXTRACT_VECTOR_ELT codegen for zvfbfa #167819

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19 changes: 9 additions & 10 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1264,11 +1264,11 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
Custom);
setOperationAction(ISD::SELECT_CC, VT, Expand);
setOperationAction({ISD::VP_SINT_TO_FP, ISD::VP_UINT_TO_FP}, VT, Custom);
setOperationAction({ISD::INSERT_VECTOR_ELT, ISD::CONCAT_VECTORS,
ISD::INSERT_SUBVECTOR, ISD::EXTRACT_SUBVECTOR,
ISD::VECTOR_DEINTERLEAVE, ISD::VECTOR_INTERLEAVE,
ISD::VECTOR_REVERSE, ISD::VECTOR_SPLICE,
ISD::VECTOR_COMPRESS},
setOperationAction({ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
ISD::CONCAT_VECTORS, ISD::INSERT_SUBVECTOR,
ISD::EXTRACT_SUBVECTOR, ISD::VECTOR_DEINTERLEAVE,
ISD::VECTOR_INTERLEAVE, ISD::VECTOR_REVERSE,
ISD::VECTOR_SPLICE, ISD::VECTOR_COMPRESS},
VT, Custom);
setOperationAction(ISD::EXPERIMENTAL_VP_SPLICE, VT, Custom);
setOperationAction(ISD::EXPERIMENTAL_VP_REVERSE, VT, Custom);
Expand All @@ -1278,9 +1278,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,

MVT EltVT = VT.getVectorElementType();
if (isTypeLegal(EltVT))
setOperationAction({ISD::SPLAT_VECTOR, ISD::EXPERIMENTAL_VP_SPLAT,
ISD::EXTRACT_VECTOR_ELT},
VT, Custom);
setOperationAction({ISD::SPLAT_VECTOR, ISD::EXPERIMENTAL_VP_SPLAT}, VT,
Custom);
else
setOperationAction({ISD::SPLAT_VECTOR, ISD::EXPERIMENTAL_VP_SPLAT},
EltVT, Custom);
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@lukel97 lukel97 Nov 13, 2025

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Not from this patch, but should this have said

Suggested change
EltVT, Custom);
VT, Custom);

Removing the else branch itself seems to have no effect on codegen anyway

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@4vtomat 4vtomat Nov 13, 2025

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I think we need this because of type legalization, otherwise it doesn't know how to soft promote the operand lol

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@topperc topperc Nov 13, 2025

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Zvfbfa implies on Zfbfmin so the element type is guaranteed to be legal. This code was copied from the Zvfbfmin handling and was not updated.

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@4vtomat 4vtomat Nov 13, 2025

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Oh thats right, we don't need this in zvfbfa case

Expand Down Expand Up @@ -10356,7 +10355,7 @@ SDValue RISCVTargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op,
}

if ((ValVT == MVT::f16 && !Subtarget.hasVInstructionsF16()) ||
ValVT == MVT::bf16) {
(ValVT == MVT::bf16 && !Subtarget.hasVInstructionsBF16())) {
// If we don't have vfmv.s.f for f16/bf16, use fmv.x.h first.
MVT IntVT = VecVT.changeTypeToInteger();
SDValue IntInsert = DAG.getNode(
Expand Down Expand Up @@ -10593,7 +10592,7 @@ SDValue RISCVTargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
}

if ((EltVT == MVT::f16 && !Subtarget.hasVInstructionsF16()) ||
EltVT == MVT::bf16) {
(EltVT == MVT::bf16 && !Subtarget.hasVInstructionsBF16())) {
// If we don't have vfmv.f.s for f16/bf16, extract to a gpr then use fmv.h.x
MVT IntVT = VecVT.changeTypeToInteger();
SDValue IntVec = DAG.getBitcast(IntVT, Vec);
Expand Down
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