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[CodeGen] Add TRI::regunits() iterating over all register units (NFC) #167901

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Merged
merged 2 commits into from
Nov 13, 2025
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[CodeGen] Add TRI::regunits() iterating over all register units (NFC) #167901

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a878dc8
[CodeGen] Add TRI::regunits() iterating over all register units (NFC)
s-barannikov Nov 12, 2025
ebe745a
Revert some changes
s-barannikov Nov 13, 2025
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8 changes: 8 additions & 0 deletions llvm/include/llvm/MC/MCRegisterInfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -16,6 +16,7 @@
#define LLVM_MC_MCREGISTERINFO_H

#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/Sequence.h"
#include "llvm/ADT/iterator.h"
#include "llvm/ADT/iterator_range.h"
#include "llvm/MC/LaneBitmask.h"
Expand Down Expand Up @@ -259,6 +260,9 @@ class LLVM_ABI MCRegisterInfo {
iterator_range<MCSuperRegIterator>>
sub_and_superregs_inclusive(MCRegister Reg) const;

/// Returns an iterator range over all regunits.
iota_range<MCRegUnit> regunits() const;

/// Returns an iterator range over all regunits for \p Reg.
iterator_range<MCRegUnitIterator> regunits(MCRegister Reg) const;

Expand Down Expand Up @@ -798,6 +802,10 @@ MCRegisterInfo::sub_and_superregs_inclusive(MCRegister Reg) const {
return concat<const MCPhysReg>(subregs_inclusive(Reg), superregs(Reg));
}

inline iota_range<MCRegUnit> MCRegisterInfo::regunits() const {
return seq(getNumRegUnits());
}

inline iterator_range<MCRegUnitIterator>
MCRegisterInfo::regunits(MCRegister Reg) const {
return make_range({Reg, this}, MCRegUnitIterator());
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/CodeGen/LiveIntervals.cpp
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Expand Up @@ -173,8 +173,8 @@ void LiveIntervals::analyze(MachineFunction &fn) {
if (EnablePrecomputePhysRegs) {
// For stress testing, precompute live ranges of all physical register
// units, including reserved registers.
for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
getRegUnit(i);
for (MCRegUnit Unit : TRI->regunits())
getRegUnit(Unit);
}
}

Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/CodeGen/LiveRegUnits.cpp
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Expand Up @@ -20,7 +20,7 @@
using namespace llvm;

void LiveRegUnits::removeRegsNotPreserved(const uint32_t *RegMask) {
for (unsigned U = 0, E = TRI->getNumRegUnits(); U != E; ++U) {
for (MCRegUnit U : TRI->regunits()) {
for (MCRegUnitRootIterator RootReg(U, TRI); RootReg.isValid(); ++RootReg) {
if (MachineOperand::clobbersPhysReg(RegMask, *RootReg)) {
Units.reset(U);
Expand All @@ -31,7 +31,7 @@ void LiveRegUnits::removeRegsNotPreserved(const uint32_t *RegMask) {
}

void LiveRegUnits::addRegsInMask(const uint32_t *RegMask) {
for (unsigned U = 0, E = TRI->getNumRegUnits(); U != E; ++U) {
for (MCRegUnit U : TRI->regunits()) {
for (MCRegUnitRootIterator RootReg(U, TRI); RootReg.isValid(); ++RootReg) {
if (MachineOperand::clobbersPhysReg(RegMask, *RootReg)) {
Units.set(U);
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/CodeGen/MachineVerifier.cpp
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Expand Up @@ -3564,9 +3564,9 @@ void MachineVerifier::verifyLiveIntervals() {
}

// Verify all the cached regunit intervals.
for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
if (const LiveRange *LR = LiveInts->getCachedRegUnit(i))
verifyLiveRange(*LR, VirtRegOrUnit(i));
for (MCRegUnit Unit : TRI->regunits())
if (const LiveRange *LR = LiveInts->getCachedRegUnit(Unit))
verifyLiveRange(*LR, VirtRegOrUnit(Unit));
}

void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/CodeGen/RDFRegisters.cpp
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Expand Up @@ -46,7 +46,7 @@ PhysicalRegisterInfo::PhysicalRegisterInfo(const TargetRegisterInfo &tri,

UnitInfos.resize(TRI.getNumRegUnits());

for (uint32_t U = 0, NU = TRI.getNumRegUnits(); U != NU; ++U) {
for (MCRegUnit U : TRI.regunits()) {
if (UnitInfos[U].Reg != 0)
continue;
MCRegUnitRootIterator R(U, &TRI);
Expand Down Expand Up @@ -88,7 +88,7 @@ PhysicalRegisterInfo::PhysicalRegisterInfo(const TargetRegisterInfo &tri,
}

AliasInfos.resize(TRI.getNumRegUnits());
for (uint32_t U = 0, NU = TRI.getNumRegUnits(); U != NU; ++U) {
for (MCRegUnit U : TRI.regunits()) {
BitVector AS(TRI.getNumRegs());
for (MCRegUnitRootIterator R(U, &TRI); R.isValid(); ++R)
for (MCPhysReg S : TRI.superregs_inclusive(*R))
Expand Down
3 changes: 1 addition & 2 deletions llvm/lib/CodeGen/RegAllocFast.cpp
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Expand Up @@ -1291,8 +1291,7 @@ bool RegAllocFastImpl::setPhysReg(MachineInstr &MI, MachineOperand &MO,
#ifndef NDEBUG

void RegAllocFastImpl::dumpState() const {
for (unsigned Unit = 1, UnitE = TRI->getNumRegUnits(); Unit != UnitE;
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@kazutakahirata kazutakahirata Nov 13, 2025

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Do we need to preserve the semantics of Unit = 1 somehow? Maybe with drop_begin?

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@s-barannikov s-barannikov Nov 13, 2025

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Good eye, answered just below

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@arsenm arsenm Nov 13, 2025

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You could also probably just apply this in regunits(). There's probably no reason to visit the invalid case

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@s-barannikov s-barannikov Nov 13, 2025

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0 is a valid regunit AFAICT (unlike MCRegister)
Let me double check

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@s-barannikov s-barannikov Nov 13, 2025 •
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Yep, it is valid.
E.g. there is an entry for regunit 0 in AMDGPURegUnitRoots; it says ASYNCcnt is the root.
MCRegisterDesc entry for ASYNCcnt also has regunit 0 encoded in RegUnits field (12 lowest bits).

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@s-barannikov s-barannikov Nov 13, 2025 •
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There was a small bug here: regunit 0 was skipped. This is a debugging function, so the change should be non-functional.

++Unit) {
for (MCRegUnit Unit : TRI->regunits()) {
switch (unsigned VirtReg = RegUnitStates[Unit]) {
case regFree:
break;
Expand Down
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