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[llvm][RISCV] Support splat and vp_splat for zvfbfa codegen #167920

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Merged
merged 4 commits into from
Nov 17, 2025
Merged

[llvm][RISCV] Support splat and vp_splat for zvfbfa codegen #167920

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67db906
[llvm][RISCV] Support splat and vp_splat for zvfbfa codegen
4vtomat Nov 13, 2025
f29042b
Merge remote-tracking branch 'origin/main' into zvfbfa_splat_vector
4vtomat Nov 14, 2025
fedf2d8
Merge remote-tracking branch 'origin/main' into zvfbfa_splat_vector
4vtomat Nov 17, 2025
f8a236e
fixup! update test
4vtomat Nov 17, 2025
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18 changes: 7 additions & 11 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -88,9 +88,10 @@ static cl::opt<bool>
cl::init(true));

// TODO: Support more ops
static const unsigned ZvfbfaVPOps[] = {ISD::VP_FNEG, ISD::VP_FABS,
ISD::VP_FCOPYSIGN};
static const unsigned ZvfbfaOps[] = {ISD::FNEG, ISD::FABS, ISD::FCOPYSIGN};
static const unsigned ZvfbfaVPOps[] = {
ISD::VP_FNEG, ISD::VP_FABS, ISD::VP_FCOPYSIGN, ISD::EXPERIMENTAL_VP_SPLAT};
static const unsigned ZvfbfaOps[] = {ISD::FNEG, ISD::FABS, ISD::FCOPYSIGN,
ISD::SPLAT_VECTOR};

RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
const RISCVSubtarget &STI)
Expand Down Expand Up @@ -1272,17 +1273,12 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
VT, Custom);
setOperationAction(ISD::EXPERIMENTAL_VP_SPLICE, VT, Custom);
setOperationAction(ISD::EXPERIMENTAL_VP_REVERSE, VT, Custom);
setOperationAction(ISD::EXPERIMENTAL_VP_SPLAT, VT, Custom);

setOperationAction(ISD::FCOPYSIGN, VT, Legal);
setOperationAction(ISD::SPLAT_VECTOR, VT, Legal);
setOperationAction(ZvfbfaVPOps, VT, Custom);

MVT EltVT = VT.getVectorElementType();
if (isTypeLegal(EltVT))
setOperationAction({ISD::SPLAT_VECTOR, ISD::EXPERIMENTAL_VP_SPLAT}, VT,
Custom);
else
setOperationAction({ISD::SPLAT_VECTOR, ISD::EXPERIMENTAL_VP_SPLAT},
EltVT, Custom);
setOperationAction({ISD::LOAD, ISD::STORE, ISD::MLOAD, ISD::MSTORE,
ISD::MGATHER, ISD::MSCATTER, ISD::VP_LOAD,
ISD::VP_STORE, ISD::EXPERIMENTAL_VP_STRIDED_LOAD,
Expand Down Expand Up @@ -4870,7 +4866,7 @@ static SDValue lowerScalarSplat(SDValue Passthru, SDValue Scalar, SDValue VL,

if (VT.isFloatingPoint()) {
if ((EltVT == MVT::f16 && !Subtarget.hasStdExtZvfh()) ||
EltVT == MVT::bf16) {
(EltVT == MVT::bf16 && !Subtarget.hasVInstructionsBF16())) {
if ((EltVT == MVT::bf16 && Subtarget.hasStdExtZfbfmin()) ||
(EltVT == MVT::f16 && Subtarget.hasStdExtZfhmin()))
Scalar = DAG.getNode(RISCVISD::FMV_X_ANYEXTH, DL, XLenVT, Scalar);
Expand Down
46 changes: 46 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat-bf16.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,8 @@
; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVFBFMIN
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfbfmin,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZFBFMIN-ZVFBFMIN
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVFBFMIN
; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+experimental-zvfbfa -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVFBFA
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+experimental-zvfbfa -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVFBFA

define <8 x bfloat> @splat_v8bf16(ptr %x, bfloat %y) {
; ZFBFMIN-ZVFBFMIN-LABEL: splat_v8bf16:
Expand All @@ -18,6 +20,12 @@ define <8 x bfloat> @splat_v8bf16(ptr %x, bfloat %y) {
; ZVFBFMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFBFMIN-NEXT: vmv.v.x v8, a0
; ZVFBFMIN-NEXT: ret
;
; ZVFBFA-LABEL: splat_v8bf16:
; ZVFBFA: # %bb.0:
; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, m1, ta, ma
; ZVFBFA-NEXT: vfmv.v.f v8, fa0
; ZVFBFA-NEXT: ret
%a = insertelement <8 x bfloat> poison, bfloat %y, i32 0
%b = shufflevector <8 x bfloat> %a, <8 x bfloat> poison, <8 x i32> zeroinitializer
ret <8 x bfloat> %b
Expand All @@ -37,6 +45,12 @@ define <16 x bfloat> @splat_16bf16(ptr %x, bfloat %y) {
; ZVFBFMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFBFMIN-NEXT: vmv.v.x v8, a0
; ZVFBFMIN-NEXT: ret
;
; ZVFBFA-LABEL: splat_16bf16:
; ZVFBFA: # %bb.0:
; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, m2, ta, ma
; ZVFBFA-NEXT: vfmv.v.f v8, fa0
; ZVFBFA-NEXT: ret
%a = insertelement <16 x bfloat> poison, bfloat %y, i32 0
%b = shufflevector <16 x bfloat> %a, <16 x bfloat> poison, <16 x i32> zeroinitializer
ret <16 x bfloat> %b
Expand All @@ -58,6 +72,12 @@ define <64 x bfloat> @splat_64bf16(ptr %x, bfloat %y) {
; ZVFBFMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; ZVFBFMIN-NEXT: vmv.v.x v8, a0
; ZVFBFMIN-NEXT: ret
;
; ZVFBFA-LABEL: splat_64bf16:
; ZVFBFA: # %bb.0:
; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, m8, ta, ma
; ZVFBFA-NEXT: vfmv.v.f v8, fa0
; ZVFBFA-NEXT: ret
%a = insertelement <64 x bfloat> poison, bfloat %y, i32 0
%b = shufflevector <64 x bfloat> %a, <64 x bfloat> poison, <64 x i32> zeroinitializer
ret <64 x bfloat> %b
Expand All @@ -75,6 +95,12 @@ define <8 x bfloat> @splat_zero_v8bf16(ptr %x) {
; ZVFBFMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFBFMIN-NEXT: vmv.v.i v8, 0
; ZVFBFMIN-NEXT: ret
;
; ZVFBFA-LABEL: splat_zero_v8bf16:
; ZVFBFA: # %bb.0:
; ZVFBFA-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVFBFA-NEXT: vmv.v.i v8, 0
; ZVFBFA-NEXT: ret
ret <8 x bfloat> splat (bfloat 0.0)
}

Expand All @@ -90,6 +116,12 @@ define <16 x bfloat> @splat_zero_16bf16(ptr %x) {
; ZVFBFMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFBFMIN-NEXT: vmv.v.i v8, 0
; ZVFBFMIN-NEXT: ret
;
; ZVFBFA-LABEL: splat_zero_16bf16:
; ZVFBFA: # %bb.0:
; ZVFBFA-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; ZVFBFA-NEXT: vmv.v.i v8, 0
; ZVFBFA-NEXT: ret
ret <16 x bfloat> splat (bfloat 0.0)
}

Expand All @@ -107,6 +139,13 @@ define <8 x bfloat> @splat_negzero_v8bf16(ptr %x) {
; ZVFBFMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFBFMIN-NEXT: vmv.v.x v8, a0
; ZVFBFMIN-NEXT: ret
;
; ZVFBFA-LABEL: splat_negzero_v8bf16:
; ZVFBFA: # %bb.0:
; ZVFBFA-NEXT: lui a0, 1048568
; ZVFBFA-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVFBFA-NEXT: vmv.v.x v8, a0
; ZVFBFA-NEXT: ret
ret <8 x bfloat> splat (bfloat -0.0)
}

Expand All @@ -124,5 +163,12 @@ define <16 x bfloat> @splat_negzero_16bf16(ptr %x) {
; ZVFBFMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFBFMIN-NEXT: vmv.v.x v8, a0
; ZVFBFMIN-NEXT: ret
;
; ZVFBFA-LABEL: splat_negzero_16bf16:
; ZVFBFA: # %bb.0:
; ZVFBFA-NEXT: lui a0, 1048568
; ZVFBFA-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; ZVFBFA-NEXT: vmv.v.x v8, a0
; ZVFBFA-NEXT: ret
ret <16 x bfloat> splat (bfloat -0.0)
}
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