[CodeGen] Turn MCRegUnit into an enum class (NFC)

llvm/include/llvm/CodeGen/LiveIntervalUnion.h

@@ -191,14 +191,14 @@ class LiveIntervalUnion {
 
     void clear();
 
-    LiveIntervalUnion& operator[](unsigned idx) {
-      assert(idx <  Size && "idx out of bounds");
-      return LIUs[idx];
+    LiveIntervalUnion &operator[](MCRegUnit Unit) {
+      assert(static_cast<unsigned>(Unit) < Size && "Unit out of bounds");
+      return LIUs[static_cast<unsigned>(Unit)];
     }
 
-    const LiveIntervalUnion& operator[](unsigned Idx) const {
-      assert(Idx < Size && "Idx out of bounds");
-      return LIUs[Idx];
+    const LiveIntervalUnion &operator[](MCRegUnit Unit) const {
+      assert(static_cast<unsigned>(Unit) < Size && "Unit out of bounds");
+      return LIUs[static_cast<unsigned>(Unit)];
     }
   };
 };

llvm/include/llvm/CodeGen/LiveIntervals.h

@@ -413,29 +413,32 @@ class LiveIntervals {
   /// Return the live range for register unit \p Unit. It will be computed if
   /// it doesn't exist.
   LiveRange &getRegUnit(MCRegUnit Unit) {
-    LiveRange *LR = RegUnitRanges[Unit];
+    LiveRange *LR = RegUnitRanges[static_cast<unsigned>(Unit)];
     if (!LR) {
       // Compute missing ranges on demand.
       // Use segment set to speed-up initial computation of the live range.
-      RegUnitRanges[Unit] = LR = new LiveRange(UseSegmentSetForPhysRegs);
+      RegUnitRanges[static_cast<unsigned>(Unit)] = LR =
+          new LiveRange(UseSegmentSetForPhysRegs);
       computeRegUnitRange(*LR, Unit);
     }
     return *LR;
   }
 
   /// Return the live range for register unit \p Unit if it has already been
   /// computed, or nullptr if it hasn't been computed yet.
-  LiveRange *getCachedRegUnit(MCRegUnit Unit) { return RegUnitRanges[Unit]; }
+  LiveRange *getCachedRegUnit(MCRegUnit Unit) {
+    return RegUnitRanges[static_cast<unsigned>(Unit)];
+  }
 
   const LiveRange *getCachedRegUnit(MCRegUnit Unit) const {
-    return RegUnitRanges[Unit];
+    return RegUnitRanges[static_cast<unsigned>(Unit)];
   }
 
   /// Remove computed live range for register unit \p Unit. Subsequent uses
   /// should rely on on-demand recomputation.
   void removeRegUnit(MCRegUnit Unit) {
-    delete RegUnitRanges[Unit];
-    RegUnitRanges[Unit] = nullptr;
+    delete RegUnitRanges[static_cast<unsigned>(Unit)];
+    RegUnitRanges[static_cast<unsigned>(Unit)] = nullptr;
   }
 
   /// Remove associated live ranges for the register units associated with \p

llvm/include/llvm/CodeGen/LiveRegMatrix.h

@@ -165,7 +165,9 @@ class LiveRegMatrix {
 
   /// Directly access the live interval unions per regunit.
   /// This returns an array indexed by the regunit number.
-  LiveIntervalUnion *getLiveUnions() { return &Matrix[0]; }
+  LiveIntervalUnion *getLiveUnions() {
+    return &Matrix[static_cast<MCRegUnit>(0)];
+  }
 
   Register getOneVReg(unsigned PhysReg) const;
 };

llvm/include/llvm/CodeGen/LiveRegUnits.h

@@ -86,23 +86,23 @@ class LiveRegUnits {
   /// Adds register units covered by physical register \p Reg.
   void addReg(MCRegister Reg) {
     for (MCRegUnit Unit : TRI->regunits(Reg))
-      Units.set(Unit);
+      Units.set(static_cast<unsigned>(Unit));
   }
 
   /// Adds register units covered by physical register \p Reg that are
   /// part of the lanemask \p Mask.
   void addRegMasked(MCRegister Reg, LaneBitmask Mask) {
-    for (MCRegUnitMaskIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) {
-      LaneBitmask UnitMask = (*Unit).second;
+    for (MCRegUnitMaskIterator I(Reg, TRI); I.isValid(); ++I) {
+      auto [Unit, UnitMask] = *I;
       if ((UnitMask & Mask).any())
-        Units.set((*Unit).first);
+        Units.set(static_cast<unsigned>(Unit));
     }
   }
 
   /// Removes all register units covered by physical register \p Reg.
   void removeReg(MCRegister Reg) {
     for (MCRegUnit Unit : TRI->regunits(Reg))
-      Units.reset(Unit);
+      Units.reset(static_cast<unsigned>(Unit));
   }
 
   /// Removes register units not preserved by the regmask \p RegMask.
@@ -116,7 +116,7 @@ class LiveRegUnits {
   /// Returns true if no part of physical register \p Reg is live.
   bool available(MCRegister Reg) const {
     for (MCRegUnit Unit : TRI->regunits(Reg)) {
-      if (Units.test(Unit))
+      if (Units.test(static_cast<unsigned>(Unit)))
         return false;
     }
     return true;

llvm/include/llvm/CodeGen/MachineTraceMetrics.h

@@ -78,12 +78,12 @@ struct LiveRegUnit {
   const MachineInstr *MI = nullptr;
   unsigned Op = 0;
 
-  unsigned getSparseSetIndex() const { return RegUnit; }
+  unsigned getSparseSetIndex() const { return static_cast<unsigned>(RegUnit); }
 
   explicit LiveRegUnit(MCRegUnit RU) : RegUnit(RU) {}
 };
 
-using LiveRegUnitSet = SparseSet<LiveRegUnit>;
+using LiveRegUnitSet = SparseSet<LiveRegUnit, MCRegUnit, MCRegUnitToIndex>;
 
 /// Strategies for selecting traces.
 enum class MachineTraceStrategy {

llvm/include/llvm/CodeGen/RDFRegisters.h

@@ -10,6 +10,7 @@
 #define LLVM_CODEGEN_RDFREGISTERS_H
 
 #include "llvm/ADT/BitVector.h"
+#include "llvm/ADT/IndexedMap.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/iterator_range.h"
 #include "llvm/CodeGen/TargetRegisterInfo.h"
@@ -111,7 +112,7 @@ struct RegisterRef {
 
   constexpr MCRegUnit asMCRegUnit() const {
     assert(isUnit());
-    return Id & ~UnitFlag;
+    return static_cast<MCRegUnit>(Id & ~UnitFlag);
   }
 
   constexpr unsigned asMaskIdx() const {
@@ -160,7 +161,7 @@ struct PhysicalRegisterInfo {
   // Returns the set of aliased physical registers.
   std::set<RegisterId> getAliasSet(RegisterRef RR) const;
 
-  RegisterRef getRefForUnit(uint32_t U) const {
+  RegisterRef getRefForUnit(MCRegUnit U) const {
     return RegisterRef(UnitInfos[U].Reg, UnitInfos[U].Mask);
   }
 
@@ -170,7 +171,7 @@ struct PhysicalRegisterInfo {
 
   std::set<RegisterId> getUnits(RegisterRef RR) const;
 
-  const BitVector &getUnitAliases(uint32_t U) const {
+  const BitVector &getUnitAliases(MCRegUnit U) const {
     return AliasInfos[U].Regs;
   }
 
@@ -201,9 +202,9 @@ struct PhysicalRegisterInfo {
   const TargetRegisterInfo &TRI;
   IndexedSet<const uint32_t *> RegMasks;
   std::vector<RegInfo> RegInfos;
-  std::vector<UnitInfo> UnitInfos;
+  IndexedMap<UnitInfo, MCRegUnitToIndex> UnitInfos;
   std::vector<MaskInfo> MaskInfos;
-  std::vector<AliasInfo> AliasInfos;
+  IndexedMap<AliasInfo, MCRegUnitToIndex> AliasInfos;
 };
 
 struct RegisterRefEqualTo {

llvm/include/llvm/CodeGen/ReachingDefAnalysis.h

@@ -78,17 +78,17 @@ class MBBReachingDefsInfo {
   }
 
   void append(unsigned MBBNumber, MCRegUnit Unit, int Def) {
-    AllReachingDefs[MBBNumber][Unit].push_back(Def);
+    AllReachingDefs[MBBNumber][static_cast<unsigned>(Unit)].push_back(Def);
   }
 
   void prepend(unsigned MBBNumber, MCRegUnit Unit, int Def) {
-    auto &Defs = AllReachingDefs[MBBNumber][Unit];
+    auto &Defs = AllReachingDefs[MBBNumber][static_cast<unsigned>(Unit)];
     Defs.insert(Defs.begin(), Def);
   }
 
   void replaceFront(unsigned MBBNumber, MCRegUnit Unit, int Def) {
-    assert(!AllReachingDefs[MBBNumber][Unit].empty());
-    *AllReachingDefs[MBBNumber][Unit].begin() = Def;
+    assert(!AllReachingDefs[MBBNumber][static_cast<unsigned>(Unit)].empty());
+    *AllReachingDefs[MBBNumber][static_cast<unsigned>(Unit)].begin() = Def;
   }
 
   void clear() { AllReachingDefs.clear(); }
@@ -97,7 +97,7 @@ class MBBReachingDefsInfo {
     if (AllReachingDefs[MBBNumber].empty())
       // Block IDs are not necessarily dense.
       return ArrayRef<ReachingDef>();
-    return AllReachingDefs[MBBNumber][Unit];
+    return AllReachingDefs[MBBNumber][static_cast<unsigned>(Unit)];
   }
 
 private:

llvm/include/llvm/CodeGen/Register.h

@@ -182,20 +182,25 @@ class VirtRegOrUnit {
   unsigned VRegOrUnit;
 
 public:
-  constexpr explicit VirtRegOrUnit(MCRegUnit Unit) : VRegOrUnit(Unit) {
+  constexpr explicit VirtRegOrUnit(MCRegUnit Unit)
+      : VRegOrUnit(static_cast<unsigned>(Unit)) {
     assert(!Register::isVirtualRegister(VRegOrUnit));
   }
+
   constexpr explicit VirtRegOrUnit(Register Reg) : VRegOrUnit(Reg.id()) {
     assert(Reg.isVirtual());
   }
 
+  // Catches implicit conversions to Register.
+  template <typename T> explicit VirtRegOrUnit(T) = delete;
+
   constexpr bool isVirtualReg() const {
     return Register::isVirtualRegister(VRegOrUnit);
   }
 
   constexpr MCRegUnit asMCRegUnit() const {
     assert(!isVirtualReg() && "Not a register unit");
-    return VRegOrUnit;
+    return static_cast<MCRegUnit>(VRegOrUnit);
   }
 
   constexpr Register asVirtualReg() const {

llvm/include/llvm/CodeGen/RegisterClassInfo.h

@@ -123,7 +123,7 @@ class RegisterClassInfo {
   MCRegister getLastCalleeSavedAlias(MCRegister PhysReg) const {
     MCRegister CSR;
     for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
-      CSR = CalleeSavedAliases[Unit];
+      CSR = CalleeSavedAliases[static_cast<unsigned>(Unit)];
       if (CSR)
         break;
     }

llvm/include/llvm/CodeGen/RegisterPressure.h

@@ -282,14 +282,14 @@ class LiveRegSet {
   unsigned getSparseIndexFromVirtRegOrUnit(VirtRegOrUnit VRegOrUnit) const {
     if (VRegOrUnit.isVirtualReg())
       return VRegOrUnit.asVirtualReg().virtRegIndex() + NumRegUnits;
-    assert(VRegOrUnit.asMCRegUnit() < NumRegUnits);
-    return VRegOrUnit.asMCRegUnit();
+    assert(static_cast<unsigned>(VRegOrUnit.asMCRegUnit()) < NumRegUnits);
+    return static_cast<unsigned>(VRegOrUnit.asMCRegUnit());
   }
 
   VirtRegOrUnit getVirtRegOrUnitFromSparseIndex(unsigned SparseIndex) const {
     if (SparseIndex >= NumRegUnits)
       return VirtRegOrUnit(Register::index2VirtReg(SparseIndex - NumRegUnits));
-    return VirtRegOrUnit(SparseIndex);
+    return VirtRegOrUnit(static_cast<MCRegUnit>(SparseIndex));
   }
 
 public:

llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h

@@ -82,14 +82,16 @@ namespace llvm {
     PhysRegSUOper(SUnit *su, int op, MCRegUnit R)
         : SU(su), OpIdx(op), RegUnit(R) {}
 
-    unsigned getSparseSetIndex() const { return RegUnit; }
+    unsigned getSparseSetIndex() const {
+      return static_cast<unsigned>(RegUnit);
+    }
   };
 
   /// Use a SparseMultiSet to track physical registers. Storage is only
   /// allocated once for the pass. It can be cleared in constant time and reused
   /// without any frees.
   using RegUnit2SUnitsMap =
-      SparseMultiSet<PhysRegSUOper, unsigned, identity, uint16_t>;
+      SparseMultiSet<PhysRegSUOper, MCRegUnit, MCRegUnitToIndex, uint16_t>;
 
   /// Track local uses of virtual registers. These uses are gathered by the DAG
   /// builder and may be consulted by the scheduler to avoid iterating an entire

llvm/include/llvm/MC/MCRegister.h

@@ -27,7 +27,15 @@ using MCPhysReg = uint16_t;
 /// A target with a complicated sub-register structure will typically have many
 /// fewer register units than actual registers. MCRI::getNumRegUnits() returns
 /// the number of register units in the target.
-using MCRegUnit = unsigned;
+enum class MCRegUnit : unsigned;
+
+struct MCRegUnitToIndex {
+  using argument_type = MCRegUnit;
+
+  unsigned operator()(MCRegUnit Unit) const {
+    return static_cast<unsigned>(Unit);
+  }
+};
 
 /// Wrapper class representing physical registers. Should be passed by value.
 class MCRegister {

llvm/include/llvm/MC/MCRegisterInfo.h

@@ -724,9 +724,10 @@ class MCRegUnitRootIterator {
   MCRegUnitRootIterator() = default;
 
   MCRegUnitRootIterator(MCRegUnit RegUnit, const MCRegisterInfo *MCRI) {
-    assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit");
-    Reg0 = MCRI->RegUnitRoots[RegUnit][0];
-    Reg1 = MCRI->RegUnitRoots[RegUnit][1];
+    assert(static_cast<unsigned>(RegUnit) < MCRI->getNumRegUnits() &&
+           "Invalid register unit");
+    Reg0 = MCRI->RegUnitRoots[static_cast<unsigned>(RegUnit)][0];
+    Reg1 = MCRI->RegUnitRoots[static_cast<unsigned>(RegUnit)][1];
   }
 
   /// Dereference to get the current root register.
@@ -803,7 +804,9 @@ MCRegisterInfo::sub_and_superregs_inclusive(MCRegister Reg) const {
 }
 
 inline iota_range<MCRegUnit> MCRegisterInfo::regunits() const {
-  return seq(getNumRegUnits());
+  return enum_seq(static_cast<MCRegUnit>(0),
+                  static_cast<MCRegUnit>(getNumRegUnits()),
+                  force_iteration_on_noniterable_enum);
 }
 
 inline iterator_range<MCRegUnitIterator>

llvm/lib/CodeGen/EarlyIfConversion.cpp

@@ -134,7 +134,7 @@ class SSAIfConv {
   BitVector ClobberedRegUnits;
 
   // Scratch pad for findInsertionPoint.
-  SparseSet<MCRegUnit> LiveRegUnits;
+  SparseSet<MCRegUnit, MCRegUnit, MCRegUnitToIndex> LiveRegUnits;
 
   /// Insertion point in Head for speculatively executed instructions form TBB
   /// and FBB.
@@ -271,7 +271,7 @@ bool SSAIfConv::InstrDependenciesAllowIfConv(MachineInstr *I) {
     // Remember clobbered regunits.
     if (MO.isDef() && Reg.isPhysical())
       for (MCRegUnit Unit : TRI->regunits(Reg.asMCReg()))
-        ClobberedRegUnits.set(Unit);
+        ClobberedRegUnits.set(static_cast<unsigned>(Unit));
 
     if (!MO.readsReg() || !Reg.isVirtual())
       continue;
@@ -409,7 +409,7 @@ bool SSAIfConv::findInsertionPoint() {
     // Anything read by I is live before I.
     while (!Reads.empty())
       for (MCRegUnit Unit : TRI->regunits(Reads.pop_back_val()))
-        if (ClobberedRegUnits.test(Unit))
+        if (ClobberedRegUnits.test(static_cast<unsigned>(Unit)))
           LiveRegUnits.insert(Unit);
 
     // We can't insert before a terminator.

llvm/lib/CodeGen/InterferenceCache.cpp

@@ -93,7 +93,7 @@ void InterferenceCache::Entry::revalidate(LiveIntervalUnion *LIUArray,
   PrevPos = SlotIndex();
   unsigned i = 0;
   for (MCRegUnit Unit : TRI->regunits(PhysReg))
-    RegUnits[i++].VirtTag = LIUArray[Unit].getTag();
+    RegUnits[i++].VirtTag = LIUArray[static_cast<unsigned>(Unit)].getTag();
 }
 
 void InterferenceCache::Entry::reset(MCRegister physReg,
@@ -110,7 +110,7 @@ void InterferenceCache::Entry::reset(MCRegister physReg,
   PrevPos = SlotIndex();
   RegUnits.clear();
   for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
-    RegUnits.push_back(LIUArray[Unit]);
+    RegUnits.push_back(LIUArray[static_cast<unsigned>(Unit)]);
     RegUnits.back().Fixed = &LIS->getRegUnit(Unit);
   }
 }
@@ -121,7 +121,7 @@ bool InterferenceCache::Entry::valid(LiveIntervalUnion *LIUArray,
   for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
     if (i == e)
       return false;
-    if (LIUArray[Unit].changedSince(RegUnits[i].VirtTag))
+    if (LIUArray[static_cast<unsigned>(Unit)].changedSince(RegUnits[i].VirtTag))
       return false;
     ++i;
   }